[PATCH] D155343: MachineSink: Fix sinking VGPR def out of a divergent loop

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D155343#4520753 <https://reviews.llvm.org/D155343#4520753>, @arsenm wrote:

> In D155343#4517032 <https://reviews.llvm.org/D155343#4517032>, @ruiling wrote:
>
>> I think a more accurate description of the real problem is: sinking vgpr def which has a loop-variant sgpr source out of divergent loop is wrong for AMDGPU. For other cases, it is still legal to move out of loop. The problem is not specific to nested loops, it also applies to single loop. The test case has been over-simplified and does not show original problem (both .ll and .mir test). We can keep the code as now, but I still think it's better to update the tests to show the real problem to make it easy to revisit the issue.
>
> What do you suggest? I think we need to come up with a way to properly model this

I was thinking about something along the lines of marking basic block edges as read or write convergent, and then adding some notion of read/write convergence that approximately means VALU, VALU cross lane, scalar or divergent control flow


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https://reviews.llvm.org/D155343