[PATCH] D155288: [RISCV] Add a new select combine for when the condition is a setcc that will be inverted

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 542519.
asb edited the summary of this revision.
asb added a comment.

Rebase now D155328 <https://reviews.llvm.org/D155328> landed.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155288/new/

https://reviews.llvm.org/D155288

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
  llvm/test/CodeGen/RISCV/compress.ll
  llvm/test/CodeGen/RISCV/condops.ll
  llvm/test/CodeGen/RISCV/double-select-icmp.ll
  llvm/test/CodeGen/RISCV/float-select-icmp.ll
  llvm/test/CodeGen/RISCV/forced-atomics.ll
  llvm/test/CodeGen/RISCV/half-select-icmp.ll
  llvm/test/CodeGen/RISCV/select-cc.ll
  llvm/test/CodeGen/RISCV/select-constant-xor.ll
  llvm/test/CodeGen/RISCV/xaluo.ll

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