[PATCH] D155840: [RISCV][NFC] Add RISCVSubtarget field to RISCVExpandPseudo and RISCVPreRAExpandPseudo

[Alex Bradbury via Phabricator via llvm-commits]

asb updated this revision to Diff 542505.
asb added a comment.

Correcting missed context.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155840/new/

https://reviews.llvm.org/D155840

Files:
  llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp


Index: llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
+++ llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp
@@ -30,6 +30,7 @@
 
 class RISCVExpandPseudo : public MachineFunctionPass {
 public:
+  const RISCVSubtarget *STI;
   const RISCVInstrInfo *TII;
   static char ID;
 
@@ -68,7 +69,8 @@
 char RISCVExpandPseudo::ID = 0;
 
 bool RISCVExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
-  TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
+  STI = &MF.getSubtarget<RISCVSubtarget>();
+  TII = STI->getInstrInfo();
 
 #ifndef NDEBUG
   const unsigned OldSize = getInstSizeInBytes(MF);
@@ -264,9 +266,8 @@
 // sequence for RV32.
 bool RISCVExpandPseudo::expandRV32ZdinxStore(MachineBasicBlock &MBB,
                                              MachineBasicBlock::iterator MBBI) {
-  MachineFunction *MF = MBB.getParent();
   DebugLoc DL = MBBI->getDebugLoc();
-  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
+  const TargetRegisterInfo *TRI = STI->getRegisterInfo();
   Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32);
   Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi);
   BuildMI(MBB, MBBI, DL, TII->get(RISCV::SW))
@@ -275,7 +276,7 @@
       .add(MBBI->getOperand(2));
   if (MBBI->getOperand(2).isGlobal() || MBBI->getOperand(2).isCPI()) {
     // FIXME: Zdinx RV32 can not work on unaligned scalar memory.
-    assert(!MF->getSubtarget<RISCVSubtarget>().enableUnalignedScalarMem());
+    assert(!STI->enableUnalignedScalarMem());
 
     assert(MBBI->getOperand(2).getOffset() % 8 == 0);
     MBBI->getOperand(2).setOffset(MBBI->getOperand(2).getOffset() + 4);
@@ -299,9 +300,8 @@
 // RV32.
 bool RISCVExpandPseudo::expandRV32ZdinxLoad(MachineBasicBlock &MBB,
                                             MachineBasicBlock::iterator MBBI) {
-  MachineFunction *MF = MBB.getParent();
   DebugLoc DL = MBBI->getDebugLoc();
-  const TargetRegisterInfo *TRI = MF->getSubtarget().getRegisterInfo();
+  const TargetRegisterInfo *TRI = STI->getRegisterInfo();
   Register Lo = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32);
   Register Hi = TRI->getSubReg(MBBI->getOperand(0).getReg(), RISCV::sub_32_hi);
 
@@ -343,6 +343,7 @@
 
 class RISCVPreRAExpandPseudo : public MachineFunctionPass {
 public:
+  const RISCVSubtarget *STI;
   const RISCVInstrInfo *TII;
   static char ID;
 
@@ -394,7 +395,8 @@
 char RISCVPreRAExpandPseudo::ID = 0;
 
 bool RISCVPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
-  TII = MF.getSubtarget<RISCVSubtarget>().getInstrInfo();
+  STI = &MF.getSubtarget<RISCVSubtarget>();
+  TII = STI->getInstrInfo();
 
 #ifndef NDEBUG
   const unsigned OldSize = getInstSizeInBytes(MF);
@@ -483,10 +485,7 @@
 bool RISCVPreRAExpandPseudo::expandLoadGlobalAddress(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     MachineBasicBlock::iterator &NextMBBI) {
-  MachineFunction *MF = MBB.getParent();
-
-  const auto &STI = MF->getSubtarget<RISCVSubtarget>();
-  unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
+  unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
   return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_GOT_HI,
                              SecondOpcode);
 }
@@ -494,10 +493,7 @@
 bool RISCVPreRAExpandPseudo::expandLoadTLSIEAddress(
     MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
     MachineBasicBlock::iterator &NextMBBI) {
-  MachineFunction *MF = MBB.getParent();
-
-  const auto &STI = MF->getSubtarget<RISCVSubtarget>();
-  unsigned SecondOpcode = STI.is64Bit() ? RISCV::LD : RISCV::LW;
+  unsigned SecondOpcode = STI->is64Bit() ? RISCV::LD : RISCV::LW;
   return expandAuipcInstPair(MBB, MBBI, NextMBBI, RISCVII::MO_TLS_GOT_HI,
                              SecondOpcode);
 }


-------------- next part --------------
A non-text attachment was scrubbed...
Name: D155840.542505.patch
Type: text/x-patch
Size: 3925 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230720/7a68cd67/attachment.bin>