[llvm] 9d138ba - [GIsel][AArch64] extend legalization of G_INSERT_VECTOR_ELT
Thorsten Schütt via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 20 04:40:06 PDT 2023
Author: Thorsten Schütt
Date: 2023-07-20T13:40:00+02:00
New Revision: 9d138baeb58136d76b244ff8102f525f47108c29
URL: https://github.com/llvm/llvm-project/commit/9d138baeb58136d76b244ff8102f525f47108c29
DIFF: https://github.com/llvm/llvm-project/commit/9d138baeb58136d76b244ff8102f525f47108c29.diff
LOG: [GIsel][AArch64] extend legalization of G_INSERT_VECTOR_ELT
Fixes https://github.com/llvm/llvm-project/issues/63826
Reviewed By: aemerson
Differential Revision: https://reviews.llvm.org/D155274
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 49ce79cefffda8..67d47f08bce6b5 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -702,7 +702,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampMaxNumElements(1, p0, 2);
getActionDefinitionsBuilder(G_INSERT_VECTOR_ELT)
- .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}));
+ .legalIf(typeInSet(0, {v16s8, v8s8, v8s16, v4s16, v4s32, v2s32, v2s64}))
+ .clampMinNumElements(0, s16, 4)
+ .clampMaxNumElements(0, s16, 8);
getActionDefinitionsBuilder(G_BUILD_VECTOR)
.legalFor({{v8s8, s8},
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
index 1dae07bd079442..26db18bd611a57 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-insert-vector-elt.mir
@@ -1,18 +1,39 @@
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=aarch64-linux-gnu -O0 -run-pass=legalizer %s -o - -global-isel-abort=1 | FileCheck %s
-
+---
+name: pr63826
+body: |
+ bb.0:
+ ; CHECK-LABEL: name: pr63826
+ ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s16>) = COPY $w0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s16) = G_CONSTANT i16 1
+ ; CHECK-NEXT: [[C1:%[0-9]+]]:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[UV:%[0-9]+]]:_(s16), [[UV1:%[0-9]+]]:_(s16) = G_UNMERGE_VALUES [[COPY]](<2 x s16>)
+ ; CHECK-NEXT: [[DEF:%[0-9]+]]:_(s16) = G_IMPLICIT_DEF
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<4 x s16>) = G_BUILD_VECTOR [[UV]](s16), [[UV1]](s16), [[DEF]](s16), [[DEF]](s16)
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[BUILD_VECTOR]], [[C]](s16), [[C1]](s32)
+ ; CHECK-NEXT: [[UV2:%[0-9]+]]:_(<2 x s16>), [[UV3:%[0-9]+]]:_(<2 x s16>) = G_UNMERGE_VALUES [[IVEC]](<4 x s16>)
+ ; CHECK-NEXT: $w0 = COPY [[UV2]](<2 x s16>)
+ %0:_(<2 x s16>) = COPY $w0
+ %1:_(s16) = G_CONSTANT i16 1
+ %2:_(s32) = G_CONSTANT i32 42
+ %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0(<2 x s16>), %1(s16), %2(s32)
+ $w0 = COPY %4(<2 x s16>)
+...
---
name: v8s8
body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s8
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: %val:_(s8) = G_CONSTANT i8 42
- ; CHECK: [[IVEC:%[0-9]+]]:_(<8 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32)
- ; CHECK: $d0 = COPY [[IVEC]](<8 x s8>)
- ; CHECK: RET_ReallyLR
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s8>) = COPY $d0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: %val:_(s8) = G_CONSTANT i8 42
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32)
+ ; CHECK-NEXT: $d0 = COPY [[IVEC]](<8 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<8 x s8>) = COPY $d0
%1:_(s32) = G_CONSTANT i32 1
%val:_(s8) = G_CONSTANT i8 42
@@ -26,12 +47,14 @@ body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v16s8
- ; CHECK: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: %val:_(s8) = G_CONSTANT i8 42
- ; CHECK: [[IVEC:%[0-9]+]]:_(<16 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32)
- ; CHECK: $q0 = COPY [[IVEC]](<16 x s8>)
- ; CHECK: RET_ReallyLR
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<16 x s8>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: %val:_(s8) = G_CONSTANT i8 42
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<16 x s8>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s8), [[C]](s32)
+ ; CHECK-NEXT: $q0 = COPY [[IVEC]](<16 x s8>)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<16 x s8>) = COPY $q0
%1:_(s32) = G_CONSTANT i32 1
%val:_(s8) = G_CONSTANT i8 42
@@ -45,12 +68,14 @@ body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v4s16
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: %val:_(s16) = G_CONSTANT i16 42
- ; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
- ; CHECK: $d0 = COPY [[IVEC]](<4 x s16>)
- ; CHECK: RET_ReallyLR
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s16>) = COPY $d0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: %val:_(s16) = G_CONSTANT i16 42
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
+ ; CHECK-NEXT: $d0 = COPY [[IVEC]](<4 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<4 x s16>) = COPY $d0
%1:_(s32) = G_CONSTANT i32 1
%val:_(s16) = G_CONSTANT i16 42
@@ -64,12 +89,14 @@ body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v8s16
- ; CHECK: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: %val:_(s16) = G_CONSTANT i16 42
- ; CHECK: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
- ; CHECK: $q0 = COPY [[IVEC]](<8 x s16>)
- ; CHECK: RET_ReallyLR
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<8 x s16>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: %val:_(s16) = G_CONSTANT i16 42
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<8 x s16>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s16), [[C]](s32)
+ ; CHECK-NEXT: $q0 = COPY [[IVEC]](<8 x s16>)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<8 x s16>) = COPY $q0
%1:_(s32) = G_CONSTANT i32 1
%val:_(s16) = G_CONSTANT i16 42
@@ -83,12 +110,14 @@ body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v2s32
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: %val:_(s32) = G_CONSTANT i32 42
- ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
- ; CHECK: $d0 = COPY [[IVEC]](<2 x s32>)
- ; CHECK: RET_ReallyLR
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s32>) = COPY $d0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: %val:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
+ ; CHECK-NEXT: $d0 = COPY [[IVEC]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<2 x s32>) = COPY $d0
%1:_(s32) = G_CONSTANT i32 1
%val:_(s32) = G_CONSTANT i32 42
@@ -102,12 +131,14 @@ body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v4s32
- ; CHECK: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: %val:_(s32) = G_CONSTANT i32 42
- ; CHECK: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
- ; CHECK: $q0 = COPY [[IVEC]](<4 x s32>)
- ; CHECK: RET_ReallyLR
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<4 x s32>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: %val:_(s32) = G_CONSTANT i32 42
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<4 x s32>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s32), [[C]](s32)
+ ; CHECK-NEXT: $q0 = COPY [[IVEC]](<4 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<4 x s32>) = COPY $q0
%1:_(s32) = G_CONSTANT i32 1
%val:_(s32) = G_CONSTANT i32 42
@@ -121,12 +152,14 @@ body: |
bb.0:
liveins: $q0
; CHECK-LABEL: name: v2s64
- ; CHECK: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
- ; CHECK: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
- ; CHECK: %val:_(s64) = G_CONSTANT i64 42
- ; CHECK: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32)
- ; CHECK: $q0 = COPY [[IVEC]](<2 x s64>)
- ; CHECK: RET_ReallyLR
+ ; CHECK: liveins: $q0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(<2 x s64>) = COPY $q0
+ ; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
+ ; CHECK-NEXT: %val:_(s64) = G_CONSTANT i64 42
+ ; CHECK-NEXT: [[IVEC:%[0-9]+]]:_(<2 x s64>) = G_INSERT_VECTOR_ELT [[COPY]], %val(s64), [[C]](s32)
+ ; CHECK-NEXT: $q0 = COPY [[IVEC]](<2 x s64>)
+ ; CHECK-NEXT: RET_ReallyLR
%0:_(<2 x s64>) = COPY $q0
%1:_(s32) = G_CONSTANT i32 1
%val:_(s64) = G_CONSTANT i64 42
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