[llvm] 7567b72 - [DAG] ShrinkDemandedConstant - early-out for empty DemandedBits/Elts

[Simon Pilgrim via llvm-commits]

Author: Simon Pilgrim
Date: 2023-07-20T12:18:10+01:00
New Revision: 7567b72f4dcf2f593f7fc8b4970e80942985495b

URL: https://github.com/llvm/llvm-project/commit/7567b72f4dcf2f593f7fc8b4970e80942985495b
DIFF: https://github.com/llvm/llvm-project/commit/7567b72f4dcf2f593f7fc8b4970e80942985495b.diff

LOG: [DAG] ShrinkDemandedConstant - early-out for empty DemandedBits/Elts

Leave this to constant folding in SimplifyDemandedBits

Fixes #63975

Added: 
    llvm/test/CodeGen/X86/pr63975.ll

Modified: 
    llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

Removed: 
    


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diff  --git a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
index 11594da0acb561..65ca0e0a22b3b9 100644
--- a/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
+++ b/llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
@@ -504,6 +504,11 @@ bool TargetLowering::ShrinkDemandedConstant(SDValue Op,
   SDLoc DL(Op);
   unsigned Opcode = Op.getOpcode();
 
+  // Early-out if we've ended up calling an undemanded node, leave this to
+  // constant folding.
+  if (DemandedBits.isZero() || DemandedElts.isZero())
+    return false;
+
   // Do target-specific constant optimization.
   if (targetShrinkDemandedConstant(Op, DemandedBits, DemandedElts, TLO))
     return TLO.New.getNode();

diff  --git a/llvm/test/CodeGen/X86/pr63975.ll b/llvm/test/CodeGen/X86/pr63975.ll
new file mode 100644
index 00000000000000..42895cbd8f43c9
--- /dev/null
+++ b/llvm/test/CodeGen/X86/pr63975.ll
@@ -0,0 +1,30 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+sse2 | FileCheck %s
+; RUN: llc < %s -mtriple=x86_64-- -mattr=+avx2 | FileCheck %s
+
+ at g = external dso_local local_unnamed_addr global i16, align 2
+ at l = external dso_local local_unnamed_addr global [1 x i16], align 2
+
+define void @PR63975() {
+; CHECK-LABEL: PR63975:
+; CHECK:       # %bb.0: # %entry
+; CHECK-NEXT:    movw $4, g(%rip)
+; CHECK-NEXT:    movw $0, l(%rip)
+; CHECK-NEXT:    retq
+entry:
+  store i16 4, ptr @g, align 2
+  %i = load i16, ptr @g, align 2
+  %broadcast.splatinsert7 = insertelement <8 x i16> poison, i16 %i, i64 0
+  %broadcast.splat8 = shufflevector <8 x i16> %broadcast.splatinsert7, <8 x i16> poison, <8 x i32> zeroinitializer
+  %i1 = and <8 x i16> %broadcast.splat8, <i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8, i16 8>
+  %i2 = or <8 x i16> %i1, <i16 246, i16 246, i16 246, i16 246, i16 246, i16 246, i16 246, i16 246>
+  %i3 = and <8 x i16> %broadcast.splat8, <i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255, i16 255>
+  %i4 = add nuw nsw <8 x i16> %i2, %i3
+  %i5 = icmp ne <8 x i16> %i4, <i16 250, i16 250, i16 250, i16 250, i16 250, i16 250, i16 250, i16 250>
+  %i6 = zext <8 x i1> %i5 to <8 x i16>
+  %i7 = zext <8 x i1> %i5 to <8 x i16>
+  %i8 = add nuw nsw <8 x i16> %i7, %i6
+  %i9 = extractelement <8 x i16> %i8, i64 2
+  store i16 %i9, ptr @l, align 2
+  ret void
+}