[llvm] 69fc6bf - [NFC][RISCV] Rewrite TableGen files using named arguments
via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 20 02:18:05 PDT 2023
Author: wangpc
Date: 2023-07-20T17:17:49+08:00
New Revision: 69fc6bf63143fc2d730e5f105055cbcaa798769d
URL: https://github.com/llvm/llvm-project/commit/69fc6bf63143fc2d730e5f105055cbcaa798769d
DIFF: https://github.com/llvm/llvm-project/commit/69fc6bf63143fc2d730e5f105055cbcaa798769d.diff
LOG: [NFC][RISCV] Rewrite TableGen files using named arguments
To simplify code and show the usage of named arguments.
Reviewed By: michaelmaitland, MaskRay
Differential Revision: https://reviews.llvm.org/D154067
Added:
Modified:
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/lib/Target/RISCV/RISCVInstrInfoD.td
llvm/lib/Target/RISCV/RISCVInstrInfoF.td
llvm/lib/Target/RISCV/RISCVInstrInfoM.td
llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
llvm/lib/Target/RISCV/RISCVScheduleV.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfo.td b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
index 20e3a61e7f38e9..a3135814947857 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -689,7 +689,7 @@ def SLLI : Shift_ri<0b00000, 0b001, "slli">;
def SRLI : Shift_ri<0b00000, 0b101, "srli">;
def SRAI : Shift_ri<0b01000, 0b101, "srai">;
-def ADD : ALU_rr<0b0000000, 0b000, "add", /*Commutable*/1>,
+def ADD : ALU_rr<0b0000000, 0b000, "add", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def SUB : ALU_rr<0b0100000, 0b000, "sub">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
@@ -701,15 +701,15 @@ def SLT : ALU_rr<0b0000000, 0b010, "slt">,
def SLTU : ALU_rr<0b0000000, 0b011, "sltu">,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
}
-def XOR : ALU_rr<0b0000000, 0b100, "xor", /*Commutable*/1>,
+def XOR : ALU_rr<0b0000000, 0b100, "xor", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
def SRL : ALU_rr<0b0000000, 0b101, "srl">,
Sched<[WriteShiftReg, ReadShiftReg, ReadShiftReg]>;
def SRA : ALU_rr<0b0100000, 0b101, "sra">,
Sched<[WriteShiftReg, ReadShiftReg, ReadShiftReg]>;
-def OR : ALU_rr<0b0000000, 0b110, "or", /*Commutable*/1>,
+def OR : ALU_rr<0b0000000, 0b110, "or", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-def AND : ALU_rr<0b0000000, 0b111, "and", /*Commutable*/1>,
+def AND : ALU_rr<0b0000000, 0b111, "and", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
@@ -803,7 +803,7 @@ def SLLIW : ShiftW_ri<0b0000000, 0b001, "slliw">;
def SRLIW : ShiftW_ri<0b0000000, 0b101, "srliw">;
def SRAIW : ShiftW_ri<0b0100000, 0b101, "sraiw">;
-def ADDW : ALUW_rr<0b0000000, 0b000, "addw", /*Commutable*/1>,
+def ADDW : ALUW_rr<0b0000000, 0b000, "addw", Commutable=1>,
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
def SUBW : ALUW_rr<0b0100000, 0b000, "subw">,
Sched<[WriteIALU32, ReadIALU32, ReadIALU32]>;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
index c86a2610b60c35..61897e9024e2f0 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoD.td
@@ -86,11 +86,11 @@ foreach Ext = DExts in {
}
let SchedRW = [WriteFAdd64, ReadFAdd64, ReadFAdd64] in {
- defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", Ext, /*Commutable*/1>;
+ defm FADD_D : FPALU_rr_frm_m<0b0000001, "fadd.d", Ext, Commutable=1>;
defm FSUB_D : FPALU_rr_frm_m<0b0000101, "fsub.d", Ext>;
}
let SchedRW = [WriteFMul64, ReadFMul64, ReadFMul64] in
- defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", Ext, /*Commutable*/1>;
+ defm FMUL_D : FPALU_rr_frm_m<0b0001001, "fmul.d", Ext, Commutable=1>;
let SchedRW = [WriteFDiv64, ReadFDiv64, ReadFDiv64] in
defm FDIV_D : FPALU_rr_frm_m<0b0001101, "fdiv.d", Ext>;
@@ -107,8 +107,8 @@ foreach Ext = DExts in {
}
let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in {
- defm FMIN_D : FPALU_rr_m<0b0010101, 0b000, "fmin.d", Ext, /*Commutable*/1>;
- defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", Ext, /*Commutable*/1>;
+ defm FMIN_D : FPALU_rr_m<0b0010101, 0b000, "fmin.d", Ext, Commutable=1>;
+ defm FMAX_D : FPALU_rr_m<0b0010101, 0b001, "fmax.d", Ext, Commutable=1>;
}
defm FCVT_S_D : FPUnaryOp_r_frm_m<0b0100000, 0b00001, Ext, Ext.F32Ty,
@@ -120,7 +120,7 @@ foreach Ext = DExts in {
Sched<[WriteFCvtF32ToF64, ReadFCvtF32ToF64]>;
let SchedRW = [WriteFCmp64, ReadFCmp64, ReadFCmp64] in {
- defm FEQ_D : FPCmp_rr_m<0b1010001, 0b010, "feq.d", Ext, /*Commutable*/1>;
+ defm FEQ_D : FPCmp_rr_m<0b1010001, 0b010, "feq.d", Ext, Commutable=1>;
defm FLT_D : FPCmp_rr_m<0b1010001, 0b001, "flt.d", Ext>;
defm FLE_D : FPCmp_rr_m<0b1010001, 0b000, "fle.d", Ext>;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
index 9ffcce1b34a3da..199436bbc4ab8d 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoF.td
@@ -269,12 +269,12 @@ foreach Ext = FExts in {
}
let SchedRW = [WriteFAdd32, ReadFAdd32, ReadFAdd32] in {
- defm FADD_S : FPALU_rr_frm_m<0b0000000, "fadd.s", Ext, /*Commutable*/1>;
+ defm FADD_S : FPALU_rr_frm_m<0b0000000, "fadd.s", Ext, Commutable=1>;
defm FSUB_S : FPALU_rr_frm_m<0b0000100, "fsub.s", Ext>;
}
let SchedRW = [WriteFMul32, ReadFMul32, ReadFMul32] in
- defm FMUL_S : FPALU_rr_frm_m<0b0001000, "fmul.s", Ext, /*Commutable*/1>;
+ defm FMUL_S : FPALU_rr_frm_m<0b0001000, "fmul.s", Ext, Commutable=1>;
let SchedRW = [WriteFDiv32, ReadFDiv32, ReadFDiv32] in
defm FDIV_S : FPALU_rr_frm_m<0b0001100, "fdiv.s", Ext>;
@@ -291,8 +291,8 @@ foreach Ext = FExts in {
}
let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in {
- defm FMIN_S : FPALU_rr_m<0b0010100, 0b000, "fmin.s", Ext, /*Commutable*/1>;
- defm FMAX_S : FPALU_rr_m<0b0010100, 0b001, "fmax.s", Ext, /*Commutable*/1>;
+ defm FMIN_S : FPALU_rr_m<0b0010100, 0b000, "fmin.s", Ext, Commutable=1>;
+ defm FMAX_S : FPALU_rr_m<0b0010100, 0b001, "fmax.s", Ext, Commutable=1>;
}
let IsSignExtendingOpW = 1 in
@@ -306,7 +306,7 @@ foreach Ext = FExts in {
Sched<[WriteFCvtF32ToI32, ReadFCvtF32ToI32]>;
let SchedRW = [WriteFCmp32, ReadFCmp32, ReadFCmp32] in {
- defm FEQ_S : FPCmp_rr_m<0b1010000, 0b010, "feq.s", Ext, /*Commutable*/1>;
+ defm FEQ_S : FPCmp_rr_m<0b1010000, 0b010, "feq.s", Ext, Commutable=1>;
defm FLT_S : FPCmp_rr_m<0b1010000, 0b001, "flt.s", Ext>;
defm FLE_S : FPCmp_rr_m<0b1010000, 0b000, "fle.s", Ext>;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
index 73bb9c1fc5be12..6c3c9a771d94b6 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoM.td
@@ -25,13 +25,13 @@ def riscv_remuw : SDNode<"RISCVISD::REMUW", SDT_RISCVIntBinOpW>;
//===----------------------------------------------------------------------===//
let Predicates = [HasStdExtMOrZmmul] in {
-def MUL : ALU_rr<0b0000001, 0b000, "mul", /*Commutable*/1>,
+def MUL : ALU_rr<0b0000001, 0b000, "mul", Commutable=1>,
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
-def MULH : ALU_rr<0b0000001, 0b001, "mulh", /*Commutable*/1>,
+def MULH : ALU_rr<0b0000001, 0b001, "mulh", Commutable=1>,
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
def MULHSU : ALU_rr<0b0000001, 0b010, "mulhsu">,
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
-def MULHU : ALU_rr<0b0000001, 0b011, "mulhu", /*Commutable*/1>,
+def MULHU : ALU_rr<0b0000001, 0b011, "mulhu", Commutable=1>,
Sched<[WriteIMul, ReadIMul, ReadIMul]>;
} // Predicates = [HasStdExtMOrZmmul]
@@ -47,7 +47,7 @@ def REMU : ALU_rr<0b0000001, 0b111, "remu">,
} // Predicates = [HasStdExtM]
let Predicates = [HasStdExtMOrZmmul, IsRV64], IsSignExtendingOpW = 1 in {
-def MULW : ALUW_rr<0b0000001, 0b000, "mulw", /*Commutable*/1>,
+def MULW : ALUW_rr<0b0000001, 0b000, "mulw", Commutable=1>,
Sched<[WriteIMul32, ReadIMul32, ReadIMul32]>;
} // Predicates = [HasStdExtMOrZmmul, IsRV64]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
index b196653a0dfe68..f8b7e32fe34c30 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
@@ -1714,7 +1714,7 @@ multiclass VPseudoUSLoad {
VLESched<LInfo>;
def "E" # eew # "_V_" # LInfo # "_MASK" :
VPseudoUSLoadMask<vreg, eew>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
VLESched<LInfo>;
}
}
@@ -1732,7 +1732,7 @@ multiclass VPseudoFFLoad {
VLFSched<LInfo>;
def "E" # eew # "FF_V_" # LInfo # "_MASK":
VPseudoUSLoadFFMask<vreg, eew>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
VLFSched<LInfo>;
}
}
@@ -1744,7 +1744,7 @@ multiclass VPseudoLoadMask {
defvar mx = mti.LMul.MX;
defvar WriteVLDM_MX = !cast<SchedWrite>("WriteVLDM_" # mx);
let VLMul = mti.LMul.value in {
- def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, /*EEW*/1>,
+ def "_V_" # mti.BX : VPseudoUSLoadNoMask<VR, EEW=1>,
Sched<[WriteVLDM_MX, ReadVLDX]>;
}
}
@@ -1760,7 +1760,7 @@ multiclass VPseudoSLoad {
VLSSched<eew, LInfo>;
def "E" # eew # "_V_" # LInfo # "_MASK" :
VPseudoSLoadMask<vreg, eew>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
+ RISCVMaskedPseudo<MaskIdx=3>,
VLSSched<eew, LInfo>;
}
}
@@ -1789,7 +1789,7 @@ multiclass VPseudoILoad<bit Ordered> {
VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
def "EI" # idxEEW # "_V_" # IdxLInfo # "_" # DataLInfo # "_MASK" :
VPseudoILoadMask<Vreg, IdxVreg, idxEEW, idxEMUL.value, Ordered, HasConstraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3>,
+ RISCVMaskedPseudo<MaskIdx=3>,
VLXSched<dataEEW, Order, DataLInfo, IdxLInfo>;
}
}
@@ -1818,7 +1818,7 @@ multiclass VPseudoStoreMask {
defvar mx = mti.LMul.MX;
defvar WriteVSTM_MX = !cast<SchedWrite>("WriteVSTM_" # mx);
let VLMul = mti.LMul.value in {
- def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, /*EEW*/1>,
+ def "_V_" # mti.BX : VPseudoUSStoreNoMask<VR, EEW=1>,
Sched<[WriteVSTM_MX, ReadVSTX]>;
}
}
@@ -1921,7 +1921,7 @@ multiclass VPseudoVID_V {
def "_V_" # m.MX : VPseudoNullaryNoMask<m.vrclass>,
Sched<[WriteVMIdxV_MX, ReadVMask]>;
def "_V_" # m.MX # "_MASK" : VPseudoNullaryMask<m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 1>,
+ RISCVMaskedPseudo<MaskIdx=1>,
Sched<[WriteVMIdxV_MX, ReadVMask]>;
}
}
@@ -1950,7 +1950,7 @@ multiclass VPseudoVIOT_M {
def "_" # m.MX : VPseudoUnaryNoMask<m.vrclass, VR, constraint>,
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
def "_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, VR, constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
Sched<[WriteVMIotV_MX, ReadVMIotV_MX, ReadVMask]>;
}
}
@@ -1985,7 +1985,7 @@ multiclass VPseudoBinary<VReg RetClass,
Constraint>;
def suffix # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+ RISCVMaskedPseudo<MaskIdx=3>;
}
}
@@ -2005,7 +2005,7 @@ multiclass VPseudoBinaryRoundingMode<VReg RetClass,
Op2Class,
Constraint,
UsesVXRM>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+ RISCVMaskedPseudo<MaskIdx=3>;
}
}
@@ -2021,7 +2021,7 @@ multiclass VPseudoBinaryM<VReg RetClass,
let ForceTailAgnostic = true in
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMOutMask<RetClass, Op1Class,
Op2Class, Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+ RISCVMaskedPseudo<MaskIdx=3>;
}
}
@@ -2038,7 +2038,7 @@ multiclass VPseudoBinaryEmul<VReg RetClass,
Constraint>;
def suffix # "_" # emul.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+ RISCVMaskedPseudo<MaskIdx=3>;
}
}
@@ -2083,7 +2083,7 @@ multiclass VPseudoBinaryFV_VV<LMULInfo m, string Constraint = "", int sew = 0> {
multiclass VPseudoBinaryFV_VV_RM<LMULInfo m, string Constraint = "", int sew = 0> {
defm _VV : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, sew,
- /* UsesVXRM = */ 0>;
+ UsesVXRM=0>;
}
multiclass VPseudoVGTR_VV_EEW<int eew, string Constraint = ""> {
@@ -2137,7 +2137,7 @@ multiclass VPseudoBinaryV_VF<LMULInfo m, FPR_Info f, string Constraint = "", int
multiclass VPseudoBinaryV_VF_RM<LMULInfo m, FPR_Info f, string Constraint = "", int sew = 0> {
defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.vrclass, m.vrclass,
f.fprclass, m, Constraint, sew,
- /* UsesVXRM = */ 0>;
+ UsesVXRM=0>;
}
multiclass VPseudoVSLD1_VF<string Constraint = ""> {
@@ -2190,8 +2190,7 @@ multiclass VPseudoBinaryW_VV<LMULInfo m> {
multiclass VPseudoBinaryW_VV_RM<LMULInfo m> {
defm _VV : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass, m.vrclass, m,
- "@earlyclobber $rd", /* sew = */ 0,
- /* UsesVXRM = */ 0>;
+ "@earlyclobber $rd", UsesVXRM=0>;
}
multiclass VPseudoBinaryW_VX<LMULInfo m> {
@@ -2209,8 +2208,7 @@ multiclass VPseudoBinaryW_VF_RM<LMULInfo m, FPR_Info f> {
defm "_V" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.vrclass,
f.fprclass, m,
"@earlyclobber $rd",
- /* sew = */ 0,
- /* UsesVXRM = */ 0>;
+ UsesVXRM=0>;
}
multiclass VPseudoBinaryW_WV<LMULInfo m> {
@@ -2222,8 +2220,7 @@ multiclass VPseudoBinaryW_WV<LMULInfo m> {
multiclass VPseudoBinaryW_WV_RM<LMULInfo m> {
defm _WV : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass, m.vrclass, m,
- "@earlyclobber $rd", /* sew = */ 0,
- /* UsesVXRM = */ 0>;
+ "@earlyclobber $rd", UsesVXRM=0>;
defm _WV : VPseudoTiedBinaryRoundingMode<m.wvrclass, m.vrclass, m,
"@earlyclobber $rd">;
}
@@ -2240,9 +2237,7 @@ multiclass VPseudoBinaryW_WF<LMULInfo m, FPR_Info f> {
multiclass VPseudoBinaryW_WF_RM<LMULInfo m, FPR_Info f> {
defm "_W" # f.FX : VPseudoBinaryRoundingMode<m.wvrclass, m.wvrclass,
f.fprclass, m,
- /* Constraint = */ "",
- /* sew = */ 0,
- /* UsesVXRM = */ 0>;
+ UsesVXRM=0>;
}
// Narrowing instructions like vnsrl/vnsra/vnclip(u) don't need @earlyclobber
@@ -2326,7 +2321,7 @@ multiclass VPseudoVMRG_FM {
def "_V" # f.FX # "M_" # mx:
VPseudoTiedBinaryCarryIn<GetVRegNoV0<m.vrclass>.R,
- m.vrclass, f.fprclass, m, /*CarryIn=*/1, "">,
+ m.vrclass, f.fprclass, m, CarryIn=1, Constraint="">,
Sched<[WriteVFMergeV_MX, ReadVFMergeV_MX, ReadVFMergeF_MX, ReadVMask]>;
}
}
@@ -2395,7 +2390,7 @@ multiclass VPseudoVCLS_V {
def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
Sched<[WriteVFClassV_MX, ReadVFClassV_MX, ReadVMask]>;
}
}
@@ -2404,7 +2399,7 @@ multiclass VPseudoVCLS_V {
multiclass VPseudoVSQR_V_RM {
foreach m = MxListF in {
defvar mx = m.MX;
- defvar sews = SchedSEWSet<m.MX, /*isF*/ 1>.val;
+ defvar sews = SchedSEWSet<m.MX, isF=1>.val;
let VLMul = m.value in
foreach e = sews in {
@@ -2417,7 +2412,7 @@ multiclass VPseudoVSQR_V_RM {
Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
ReadVMask]>;
def "_V" # suffix # "_MASK" : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
Sched<[WriteVFSqrtV_MX_E, ReadVFSqrtV_MX_E,
ReadVMask]>;
}
@@ -2435,7 +2430,7 @@ multiclass VPseudoVRCP_V {
def "_V_" # mx : VPseudoUnaryNoMask<m.vrclass, m.vrclass>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
def "_V_" # mx # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
}
}
@@ -2451,7 +2446,7 @@ multiclass VPseudoVRCP_V_RM {
def "_V_" # mx : VPseudoUnaryNoMaskRoundingMode<m.vrclass, m.vrclass>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
def "_V_" # mx # "_MASK" : VPseudoUnaryMaskRoundingMode<m.vrclass, m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
Sched<[WriteVFRecpV_MX, ReadVFRecpV_MX, ReadVMask]>;
}
}
@@ -2469,7 +2464,7 @@ multiclass PseudoVEXT_VF2 {
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f2vrclass, constraints>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
}
@@ -2487,7 +2482,7 @@ multiclass PseudoVEXT_VF4 {
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f4vrclass, constraints>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
}
@@ -2505,7 +2500,7 @@ multiclass PseudoVEXT_VF8 {
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
def "_" # mx # "_MASK" :
VPseudoUnaryMask<m.vrclass, m.f8vrclass, constraints>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>,
+ RISCVMaskedPseudo<MaskIdx=2>,
Sched<[WriteVExtV_MX, ReadVExtV_MX, ReadVMask]>;
}
}
@@ -2763,7 +2758,7 @@ multiclass VPseudoVFMUL_VV_VF_RM {
multiclass VPseudoVFDIV_VV_VF_RM {
foreach m = MxListF in {
defvar mx = m.MX;
- defvar sews = SchedSEWSet<mx, /*isF*/ 1>.val;
+ defvar sews = SchedSEWSet<mx, isF=1>.val;
foreach e = sews in {
defvar WriteVFDivV_MX_E = !cast<SchedWrite>("WriteVFDivV_" # mx # "_E" # e);
defvar ReadVFDivV_MX_E = !cast<SchedRead>("ReadVFDivV_" # mx # "_E" # e);
@@ -3127,11 +3122,11 @@ multiclass VPseudoVCALUM_VM_XM_IM<string Constraint> {
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
- defm "" : VPseudoBinaryV_VM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_XM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_IM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUI_MX, ReadVICALUV_MX, ReadVMask]>;
}
}
@@ -3144,9 +3139,9 @@ multiclass VPseudoVCALUM_VM_XM<string Constraint> {
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
- defm "" : VPseudoBinaryV_VM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX, ReadVMask]>;
- defm "" : VPseudoBinaryV_XM<m, /*CarryOut=*/1, /*CarryIn=*/1, Constraint>,
+ defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=1, Constraint=Constraint>,
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX, ReadVMask]>;
}
}
@@ -3160,11 +3155,11 @@ multiclass VPseudoVCALUM_V_X_I<string Constraint> {
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
- defm "" : VPseudoBinaryV_VM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX]>;
- defm "" : VPseudoBinaryV_XM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX]>;
- defm "" : VPseudoBinaryV_IM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ defm "" : VPseudoBinaryV_IM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
Sched<[WriteVICALUI_MX, ReadVICALUV_MX]>;
}
}
@@ -3177,9 +3172,9 @@ multiclass VPseudoVCALUM_V_X<string Constraint> {
defvar ReadVICALUV_MX = !cast<SchedRead>("ReadVICALUV_" # mx);
defvar ReadVICALUX_MX = !cast<SchedRead>("ReadVICALUX_" # mx);
- defm "" : VPseudoBinaryV_VM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ defm "" : VPseudoBinaryV_VM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
Sched<[WriteVICALUV_MX, ReadVICALUV_MX, ReadVICALUV_MX]>;
- defm "" : VPseudoBinaryV_XM<m, /*CarryOut=*/1, /*CarryIn=*/0, Constraint>,
+ defm "" : VPseudoBinaryV_XM<m, CarryOut=1, CarryIn=0, Constraint=Constraint>,
Sched<[WriteVICALUX_MX, ReadVICALUV_MX, ReadVICALUX_MX]>;
}
}
@@ -3264,7 +3259,7 @@ multiclass VPseudoTernaryWithPolicy<VReg RetClass,
let isCommutable = Commutable in
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+ RISCVMaskedPseudo<MaskIdx=3>;
}
}
@@ -3282,36 +3277,36 @@ multiclass VPseudoTernaryWithPolicyRoundingMode<VReg RetClass,
def "_" # MInfo.MX # "_MASK" :
VPseudoBinaryMaskPolicyRoundingMode<RetClass, Op1Class,
Op2Class, Constraint,
- /* UsesVXRM = */ 0>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+ UsesVXRM_=0>,
+ RISCVMaskedPseudo<MaskIdx=3>;
}
}
multiclass VPseudoTernaryV_VV_AAXA<LMULInfo m, string Constraint = ""> {
defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
- Constraint, /*Commutable*/1>;
+ Constraint, Commutable=1>;
}
multiclass VPseudoTernaryV_VV_AAXA_RM<LMULInfo m, string Constraint = ""> {
defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,
- Constraint, /*Commutable*/1>;
+ Constraint, Commutable=1>;
}
multiclass VPseudoTernaryV_VX_AAXA<LMULInfo m, string Constraint = ""> {
defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m,
- Constraint, /*Commutable*/1>;
+ Constraint, Commutable=1>;
}
multiclass VPseudoTernaryV_VF_AAXA<LMULInfo m, FPR_Info f, string Constraint = ""> {
defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.vrclass, f.fprclass,
m.vrclass, m, Constraint,
- /*Commutable*/1>;
+ Commutable=1>;
}
multiclass VPseudoTernaryV_VF_AAXA_RM<LMULInfo m, FPR_Info f, string Constraint = ""> {
defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, f.fprclass,
m.vrclass, m, Constraint,
- /*Commutable*/1>;
+ Commutable=1>;
}
multiclass VPseudoTernaryW_VV<LMULInfo m> {
@@ -3352,7 +3347,7 @@ multiclass VPseudoVSLDVWithPolicy<VReg RetClass,
let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
+ RISCVMaskedPseudo<MaskIdx=3>;
}
}
@@ -3610,7 +3605,7 @@ multiclass VPseudoVREDMINMAX_VS {
multiclass VPseudoVWRED_VS {
foreach m = MxListWRed in {
defvar mx = m.MX;
- foreach e = SchedSEWSet<mx, /*isF*/ 0, /*isWidening*/ 1>.val in {
+ foreach e = SchedSEWSet<mx, isWidening=1>.val in {
defvar WriteVIWRedV_From_MX_E = !cast<SchedWrite>("WriteVIWRedV_From_" # mx # "_E" # e);
defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
Sched<[WriteVIWRedV_From_MX_E, ReadVIWRedV, ReadVIWRedV,
@@ -3622,7 +3617,7 @@ multiclass VPseudoVWRED_VS {
multiclass VPseudoVFRED_VS_RM {
foreach m = MxListF in {
defvar mx = m.MX;
- foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
+ foreach e = SchedSEWSet<mx, isF=1>.val in {
defvar WriteVFRedV_From_MX_E = !cast<SchedWrite>("WriteVFRedV_From_" # mx # "_E" # e);
defm _VS
: VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
@@ -3636,7 +3631,7 @@ multiclass VPseudoVFRED_VS_RM {
multiclass VPseudoVFREDMINMAX_VS {
foreach m = MxListF in {
defvar mx = m.MX;
- foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
+ foreach e = SchedSEWSet<mx, isF=1>.val in {
defvar WriteVFRedMinMaxV_From_MX_E = !cast<SchedWrite>("WriteVFRedMinMaxV_From_" # mx # "_E" # e);
defm _VS : VPseudoTernaryWithTailPolicy<V_M1.vrclass, m.vrclass, V_M1.vrclass, m, e>,
Sched<[WriteVFRedMinMaxV_From_MX_E, ReadVFRedV, ReadVFRedV, ReadVFRedV,
@@ -3648,7 +3643,7 @@ multiclass VPseudoVFREDMINMAX_VS {
multiclass VPseudoVFREDO_VS_RM {
foreach m = MxListF in {
defvar mx = m.MX;
- foreach e = SchedSEWSet<mx, /*isF*/ 1>.val in {
+ foreach e = SchedSEWSet<mx, isF=1>.val in {
defvar WriteVFRedOV_From_MX_E = !cast<SchedWrite>("WriteVFRedOV_From_" # mx # "_E" # e);
defm _VS : VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
V_M1.vrclass, m, e>,
@@ -3661,7 +3656,7 @@ multiclass VPseudoVFREDO_VS_RM {
multiclass VPseudoVFWRED_VS_RM {
foreach m = MxListFWRed in {
defvar mx = m.MX;
- foreach e = SchedSEWSet<mx, /*isF*/ 1, /*isWidening*/ 1>.val in {
+ foreach e = SchedSEWSet<mx, isF=1, isWidening=1>.val in {
defvar WriteVFWRedV_From_MX_E = !cast<SchedWrite>("WriteVFWRedV_From_" # mx # "_E" # e);
defm _VS
: VPseudoTernaryWithTailPolicyRoundingMode<V_M1.vrclass, m.vrclass,
@@ -3680,7 +3675,7 @@ multiclass VPseudoConversion<VReg RetClass,
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask<RetClass, Op1Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
+ RISCVMaskedPseudo<MaskIdx=2>;
}
}
@@ -3692,7 +3687,7 @@ multiclass VPseudoConversionRoundingMode<VReg RetClass,
def "_" # MInfo.MX : VPseudoUnaryNoMaskRoundingMode<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskRoundingMode<RetClass, Op1Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
+ RISCVMaskedPseudo<MaskIdx=2>;
}
}
@@ -3706,7 +3701,7 @@ multiclass VPseudoConversionRM<VReg RetClass,
Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMask_FRM<RetClass, Op1Class,
Constraint>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
+ RISCVMaskedPseudo<MaskIdx=2>;
}
}
@@ -5625,9 +5620,9 @@ multiclass VPatBinaryV_VM_XM_IM<string intrinsic, string instruction>
VPatBinaryV_IM_TAIL<intrinsic, instruction>;
multiclass VPatBinaryM_VM_XM_IM<string intrinsic, string instruction>
- : VPatBinaryV_VM<intrinsic, instruction, /*CarryOut=*/1>,
- VPatBinaryV_XM<intrinsic, instruction, /*CarryOut=*/1>,
- VPatBinaryV_IM<intrinsic, instruction, /*CarryOut=*/1>;
+ : VPatBinaryV_VM<intrinsic, instruction, CarryOut=1>,
+ VPatBinaryV_XM<intrinsic, instruction, CarryOut=1>,
+ VPatBinaryV_IM<intrinsic, instruction, CarryOut=1>;
multiclass VPatBinaryM_V_X_I<string intrinsic, string instruction>
: VPatBinaryV_V<intrinsic, instruction>,
@@ -5639,8 +5634,8 @@ multiclass VPatBinaryV_VM_XM<string intrinsic, string instruction>
VPatBinaryV_XM_TAIL<intrinsic, instruction>;
multiclass VPatBinaryM_VM_XM<string intrinsic, string instruction>
- : VPatBinaryV_VM<intrinsic, instruction, /*CarryOut=*/1>,
- VPatBinaryV_XM<intrinsic, instruction, /*CarryOut=*/1>;
+ : VPatBinaryV_VM<intrinsic, instruction, CarryOut=1>,
+ VPatBinaryV_XM<intrinsic, instruction, CarryOut=1>;
multiclass VPatBinaryM_V_X<string intrinsic, string instruction>
: VPatBinaryV_V<intrinsic, instruction>,
@@ -6270,10 +6265,10 @@ defm PseudoVSS : VPseudoSStore;
//===----------------------------------------------------------------------===//
// Vector Indexed Loads and Stores
-defm PseudoVLUX : VPseudoILoad</*Ordered=*/false>;
-defm PseudoVLOX : VPseudoILoad</*Ordered=*/true>;
-defm PseudoVSOX : VPseudoIStore</*Ordered=*/true>;
-defm PseudoVSUX : VPseudoIStore</*Ordered=*/false>;
+defm PseudoVLUX : VPseudoILoad<Ordered=false>;
+defm PseudoVLOX : VPseudoILoad<Ordered=true>;
+defm PseudoVSOX : VPseudoIStore<Ordered=true>;
+defm PseudoVSUX : VPseudoIStore<Ordered=false>;
//===----------------------------------------------------------------------===//
// 7.7. Unit-stride Fault-Only-First Loads
@@ -6288,12 +6283,12 @@ defm PseudoVL : VPseudoFFLoad;
//===----------------------------------------------------------------------===//
defm PseudoVLSEG : VPseudoUSSegLoad;
defm PseudoVLSSEG : VPseudoSSegLoad;
-defm PseudoVLOXSEG : VPseudoISegLoad</*Ordered=*/true>;
-defm PseudoVLUXSEG : VPseudoISegLoad</*Ordered=*/false>;
+defm PseudoVLOXSEG : VPseudoISegLoad<Ordered=true>;
+defm PseudoVLUXSEG : VPseudoISegLoad<Ordered=false>;
defm PseudoVSSEG : VPseudoUSSegStore;
defm PseudoVSSSEG : VPseudoSSegStore;
-defm PseudoVSOXSEG : VPseudoISegStore</*Ordered=*/true>;
-defm PseudoVSUXSEG : VPseudoISegStore</*Ordered=*/false>;
+defm PseudoVSOXSEG : VPseudoISegStore<Ordered=true>;
+defm PseudoVSUXSEG : VPseudoISegStore<Ordered=false>;
// vlseg<nf>e<eew>ff.v may update VL register
let hasSideEffects = 1, Defs = [VL] in {
@@ -6923,7 +6918,8 @@ let Predicates = [HasVInstructionsAnyF] in {
// 16.4. Vector Register Gather Instructions
//===----------------------------------------------------------------------===//
defm PseudoVRGATHER : VPseudoVGTR_VV_VX_VI<uimm5, "@earlyclobber $rd">;
-defm PseudoVRGATHEREI16 : VPseudoVGTR_VV_EEW</* eew */ 16, "@earlyclobber $rd">;
+defm PseudoVRGATHEREI16 : VPseudoVGTR_VV_EEW<eew=16,
+ Constraint="@earlyclobber $rd">;
//===----------------------------------------------------------------------===//
// 16.5. Vector Compress Instruction
@@ -7100,10 +7096,10 @@ let Predicates = [HasVInstructionsFullMultiply] in {
//===----------------------------------------------------------------------===//
// 11.11. Vector Integer Divide Instructions
//===----------------------------------------------------------------------===//
-defm : VPatBinaryV_VV_VX<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors, /*isSEWAware*/ 1>;
-defm : VPatBinaryV_VV_VX<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors, /*isSEWAware*/ 1>;
-defm : VPatBinaryV_VV_VX<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors, /*isSEWAware*/ 1>;
-defm : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors, /*isSEWAware*/ 1>;
+defm : VPatBinaryV_VV_VX<"int_riscv_vdivu", "PseudoVDIVU", AllIntegerVectors, isSEWAware=1>;
+defm : VPatBinaryV_VV_VX<"int_riscv_vdiv", "PseudoVDIV", AllIntegerVectors, isSEWAware=1>;
+defm : VPatBinaryV_VV_VX<"int_riscv_vremu", "PseudoVREMU", AllIntegerVectors, isSEWAware=1>;
+defm : VPatBinaryV_VV_VX<"int_riscv_vrem", "PseudoVREM", AllIntegerVectors, isSEWAware=1>;
//===----------------------------------------------------------------------===//
// 11.12. Vector Widening Integer Multiply Instructions
@@ -7229,9 +7225,9 @@ defm : VPatBinaryW_WV_WX_RM<"int_riscv_vfwsub_w", "PseudoVFWSUB",
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfmul", "PseudoVFMUL",
AllFloatVectors>;
defm : VPatBinaryV_VV_VX_RM<"int_riscv_vfdiv", "PseudoVFDIV",
- AllFloatVectors, /*isSEWAware*/ 1>;
+ AllFloatVectors, isSEWAware=1>;
defm : VPatBinaryV_VX_RM<"int_riscv_vfrdiv", "PseudoVFRDIV",
- AllFloatVectors, /*isSEWAware*/ 1>;
+ AllFloatVectors, isSEWAware=1>;
//===----------------------------------------------------------------------===//
// 13.5. Vector Widening Floating-Point Multiply
@@ -7266,7 +7262,7 @@ defm : VPatTernaryW_VV_VX_RM<"int_riscv_vfwnmsac", "PseudoVFWNMSAC",
//===----------------------------------------------------------------------===//
// 13.8. Vector Floating-Point Square-Root Instruction
//===----------------------------------------------------------------------===//
-defm : VPatUnaryV_V_RM<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors, /*isSEWAware*/ 1>;
+defm : VPatUnaryV_V_RM<"int_riscv_vfsqrt", "PseudoVFSQRT", AllFloatVectors, isSEWAware=1>;
//===----------------------------------------------------------------------===//
// 13.9. Vector Floating-Point Reciprocal Square-Root Estimate Instruction
@@ -7404,16 +7400,16 @@ defm : VPatReductionW_VS<"int_riscv_vwredsum", "PseudoVWREDSUM">;
//===----------------------------------------------------------------------===//
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
-defm : VPatReductionV_VS_RM<"int_riscv_vfredosum", "PseudoVFREDOSUM", /*IsFloat=*/1>;
-defm : VPatReductionV_VS_RM<"int_riscv_vfredusum", "PseudoVFREDUSUM", /*IsFloat=*/1>;
-defm : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", /*IsFloat=*/1>;
-defm : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", /*IsFloat=*/1>;
+defm : VPatReductionV_VS_RM<"int_riscv_vfredosum", "PseudoVFREDOSUM", IsFloat=1>;
+defm : VPatReductionV_VS_RM<"int_riscv_vfredusum", "PseudoVFREDUSUM", IsFloat=1>;
+defm : VPatReductionV_VS<"int_riscv_vfredmin", "PseudoVFREDMIN", IsFloat=1>;
+defm : VPatReductionV_VS<"int_riscv_vfredmax", "PseudoVFREDMAX", IsFloat=1>;
//===----------------------------------------------------------------------===//
// 14.4. Vector Widening Floating-Point Reduction Instructions
//===----------------------------------------------------------------------===//
-defm : VPatReductionW_VS_RM<"int_riscv_vfwredusum", "PseudoVFWREDUSUM", /*IsFloat=*/1>;
-defm : VPatReductionW_VS_RM<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", /*IsFloat=*/1>;
+defm : VPatReductionW_VS_RM<"int_riscv_vfwredusum", "PseudoVFWREDUSUM", IsFloat=1>;
+defm : VPatReductionW_VS_RM<"int_riscv_vfwredosum", "PseudoVFWREDOSUM", IsFloat=1>;
//===----------------------------------------------------------------------===//
// 15. Vector Mask Instructions
@@ -7526,12 +7522,12 @@ defm : VPatBinaryV_VX<"int_riscv_vfslide1down", "PseudoVFSLIDE1DOWN", AllFloatVe
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllIntegerVectors, uimm5>;
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
- /* eew */ 16, AllIntegerVectors>;
+ eew=16, vtilist=AllIntegerVectors>;
defm : VPatBinaryV_VV_VX_VI_INT<"int_riscv_vrgather", "PseudoVRGATHER",
AllFloatVectors, uimm5>;
defm : VPatBinaryV_VV_INT_EEW<"int_riscv_vrgatherei16_vv", "PseudoVRGATHEREI16",
- /* eew */ 16, AllFloatVectors>;
+ eew=16, vtilist=AllFloatVectors>;
//===----------------------------------------------------------------------===//
// 16.5. Vector Compress Instruction
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
index 8977bcc2d4eebe..4141c7698bb408 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td
@@ -1046,10 +1046,10 @@ let Predicates = [HasVInstructionsFullMultiply] in {
}
// 11.11. Vector Integer Divide Instructions
-defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU", AllIntegerVectors, /*isSEWAware*/ 1>;
-defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV", AllIntegerVectors, /*isSEWAware*/ 1>;
-defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU", AllIntegerVectors, /*isSEWAware*/ 1>;
-defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM", AllIntegerVectors, /*isSEWAware*/ 1>;
+defm : VPatBinarySDNode_VV_VX<udiv, "PseudoVDIVU", isSEWAware=1>;
+defm : VPatBinarySDNode_VV_VX<sdiv, "PseudoVDIV", isSEWAware=1>;
+defm : VPatBinarySDNode_VV_VX<urem, "PseudoVREMU", isSEWAware=1>;
+defm : VPatBinarySDNode_VV_VX<srem, "PseudoVREM", isSEWAware=1>;
// 11.12. Vector Widening Integer Multiply Instructions
defm : VPatWidenBinarySDNode_VV_VX<mul, sext_oneuse, sext_oneuse,
@@ -1162,8 +1162,8 @@ defm : VPatWidenBinaryFPSDNode_VV_VF_WV_WF_RM<fsub, "PseudoVFWSUB">;
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm : VPatBinaryFPSDNode_VV_VF_RM<any_fmul, "PseudoVFMUL">;
-defm : VPatBinaryFPSDNode_VV_VF_RM<any_fdiv, "PseudoVFDIV", /*isSEWAware*/ 1>;
-defm : VPatBinaryFPSDNode_R_VF_RM<any_fdiv, "PseudoVFRDIV", /*isSEWAware*/ 1>;
+defm : VPatBinaryFPSDNode_VV_VF_RM<any_fdiv, "PseudoVFDIV", isSEWAware=1>;
+defm : VPatBinaryFPSDNode_R_VF_RM<any_fdiv, "PseudoVFRDIV", isSEWAware=1>;
// 13.5. Vector Widening Floating-Point Multiply Instructions
defm : VPatWidenBinaryFPSDNode_VV_VF_RM<fmul, "PseudoVFWMUL">;
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
index 93647d8f7f8792..b433f3fb63f94c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
@@ -2197,10 +2197,10 @@ let Predicates = [HasVInstructionsFullMultiply] in {
}
// 11.11. Vector Integer Divide Instructions
-defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU", AllIntegerVectors, /*isSEWAware*/ 1>;
-defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV", AllIntegerVectors, /*isSEWAware*/ 1>;
-defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU", AllIntegerVectors, /*isSEWAware*/ 1>;
-defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM", AllIntegerVectors, /*isSEWAware*/ 1>;
+defm : VPatBinaryVL_VV_VX<riscv_udiv_vl, "PseudoVDIVU", isSEWAware=1>;
+defm : VPatBinaryVL_VV_VX<riscv_sdiv_vl, "PseudoVDIV", isSEWAware=1>;
+defm : VPatBinaryVL_VV_VX<riscv_urem_vl, "PseudoVREMU", isSEWAware=1>;
+defm : VPatBinaryVL_VV_VX<riscv_srem_vl, "PseudoVREM", isSEWAware=1>;
// 11.12. Vector Widening Integer Multiply Instructions
defm : VPatBinaryWVL_VV_VX<riscv_vwmul_vl, "PseudoVWMUL">;
@@ -2327,8 +2327,8 @@ defm : VPatBinaryFPWVL_VV_VF_WV_WF_RM<riscv_vfwsub_vl, riscv_vfwsub_w_vl, "Pseud
// 13.4. Vector Single-Width Floating-Point Multiply/Divide Instructions
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fmul_vl, "PseudoVFMUL">;
-defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fdiv_vl, "PseudoVFDIV", /*isSEWAware*/ 1>;
-defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fdiv_vl, "PseudoVFRDIV", /*isSEWAware*/ 1>;
+defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fdiv_vl, "PseudoVFDIV", isSEWAware=1>;
+defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fdiv_vl, "PseudoVFRDIV", isSEWAware=1>;
// 13.5. Vector Widening Floating-Point Multiply Instructions
defm : VPatBinaryFPWVL_VV_VF_RM<riscv_vfwmul_vl, "PseudoVFWMUL">;
@@ -2617,39 +2617,39 @@ foreach fvtiToFWti = AllWidenableFloatVectors in {
// 14. Vector Reduction Operations
// 14.1. Vector Single-Width Integer Reduction Instructions
-defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", /*is_float*/0>;
-defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", /*is_float*/0>;
-defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", /*is_float*/0>;
-defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", /*is_float*/0>;
-defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", /*is_float*/0>;
-defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", /*is_float*/0>;
-defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", /*is_float*/0>;
-defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", /*is_float*/0>;
+defm : VPatReductionVL<rvv_vecreduce_ADD_vl, "PseudoVREDSUM", is_float=0>;
+defm : VPatReductionVL<rvv_vecreduce_UMAX_vl, "PseudoVREDMAXU", is_float=0>;
+defm : VPatReductionVL<rvv_vecreduce_SMAX_vl, "PseudoVREDMAX", is_float=0>;
+defm : VPatReductionVL<rvv_vecreduce_UMIN_vl, "PseudoVREDMINU", is_float=0>;
+defm : VPatReductionVL<rvv_vecreduce_SMIN_vl, "PseudoVREDMIN", is_float=0>;
+defm : VPatReductionVL<rvv_vecreduce_AND_vl, "PseudoVREDAND", is_float=0>;
+defm : VPatReductionVL<rvv_vecreduce_OR_vl, "PseudoVREDOR", is_float=0>;
+defm : VPatReductionVL<rvv_vecreduce_XOR_vl, "PseudoVREDXOR", is_float=0>;
// 14.2. Vector Widening Integer Reduction Instructions
-defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, anyext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>;
-defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, zext_oneuse, "PseudoVWREDSUMU", /*is_float*/0>;
-defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_zext_vl_oneuse, "PseudoVWREDSUMU", /*is_float*/0>;
-defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM", /*is_float*/0>;
-defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", /*is_float*/0>;
+defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, anyext_oneuse, "PseudoVWREDSUMU", is_float=0>;
+defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, zext_oneuse, "PseudoVWREDSUMU", is_float=0>;
+defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_zext_vl_oneuse, "PseudoVWREDSUMU", is_float=0>;
+defm : VPatWidenReductionVL<rvv_vecreduce_ADD_vl, sext_oneuse, "PseudoVWREDSUM", is_float=0>;
+defm : VPatWidenReductionVL_Ext_VL<rvv_vecreduce_ADD_vl, riscv_sext_vl_oneuse, "PseudoVWREDSUM", is_float=0>;
// 14.3. Vector Single-Width Floating-Point Reduction Instructions
-defm : VPatReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", /*is_float*/1>;
-defm : VPatReductionVL_RM<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", /*is_float*/1>;
-defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", /*is_float*/1>;
-defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", /*is_float*/1>;
+defm : VPatReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, "PseudoVFREDOSUM", is_float=1>;
+defm : VPatReductionVL_RM<rvv_vecreduce_FADD_vl, "PseudoVFREDUSUM", is_float=1>;
+defm : VPatReductionVL<rvv_vecreduce_FMIN_vl, "PseudoVFREDMIN", is_float=1>;
+defm : VPatReductionVL<rvv_vecreduce_FMAX_vl, "PseudoVFREDMAX", is_float=1>;
// 14.4. Vector Widening Floating-Point Reduction Instructions
defm : VPatWidenReductionVL_RM<rvv_vecreduce_SEQ_FADD_vl, fpext_oneuse,
- "PseudoVFWREDOSUM", /*is_float*/1>;
+ "PseudoVFWREDOSUM", is_float=1>;
defm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_SEQ_FADD_vl,
riscv_fpextend_vl_oneuse,
- "PseudoVFWREDOSUM", /*is_float*/1>;
+ "PseudoVFWREDOSUM", is_float=1>;
defm : VPatWidenReductionVL_RM<rvv_vecreduce_FADD_vl, fpext_oneuse,
- "PseudoVFWREDUSUM", /*is_float*/1>;
+ "PseudoVFWREDUSUM", is_float=1>;
defm : VPatWidenReductionVL_Ext_VL_RM<rvv_vecreduce_FADD_vl,
riscv_fpextend_vl_oneuse,
- "PseudoVFWREDUSUM", /*is_float*/1>;
+ "PseudoVFWREDUSUM", is_float=1>;
// 15. Vector Mask Instructions
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 6bf58d2b46e2ff..caeedfa652e435 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -400,25 +400,25 @@ def SEXT_H : RVBUnary<0b0110000, 0b00101, 0b001, OPC_OP_IMM, "sext.h">,
} // Predicates = [HasStdExtZbb]
let Predicates = [HasStdExtZbc] in {
-def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr", /*Commutable*/1>,
+def CLMULR : ALU_rr<0b0000101, 0b010, "clmulr", Commutable=1>,
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
} // Predicates = [HasStdExtZbc]
let Predicates = [HasStdExtZbcOrZbkc] in {
-def CLMUL : ALU_rr<0b0000101, 0b001, "clmul", /*Commutable*/1>,
+def CLMUL : ALU_rr<0b0000101, 0b001, "clmul", Commutable=1>,
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
-def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh", /*Commutable*/1>,
+def CLMULH : ALU_rr<0b0000101, 0b011, "clmulh", Commutable=1>,
Sched<[WriteCLMUL, ReadCLMUL, ReadCLMUL]>;
} // Predicates = [HasStdExtZbcOrZbkc]
let Predicates = [HasStdExtZbb] in {
-def MIN : ALU_rr<0b0000101, 0b100, "min", /*Commutable*/1>,
+def MIN : ALU_rr<0b0000101, 0b100, "min", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-def MINU : ALU_rr<0b0000101, 0b101, "minu", /*Commutable*/1>,
+def MINU : ALU_rr<0b0000101, 0b101, "minu", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-def MAX : ALU_rr<0b0000101, 0b110, "max", /*Commutable*/1>,
+def MAX : ALU_rr<0b0000101, 0b110, "max", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
-def MAXU : ALU_rr<0b0000101, 0b111, "maxu", /*Commutable*/1>,
+def MAXU : ALU_rr<0b0000101, 0b111, "maxu", Commutable=1>,
Sched<[WriteIALU, ReadIALU, ReadIALU]>;
} // Predicates = [HasStdExtZbb]
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
index 98989d14a0299d..977178d99e0fc9 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
@@ -89,8 +89,8 @@ def FLI_S : FPUnaryOp_imm<0b1111000, 0b00001, 0b000, OPC_OP_FP, (outs FPR32:$rd)
Sched<[WriteFLI32]>;
let SchedRW = [WriteFMinMax32, ReadFMinMax32, ReadFMinMax32] in {
-def FMINM_S: FPALU_rr<0b0010100, 0b010, "fminm.s", FPR32, /*Commutable*/ 1>;
-def FMAXM_S: FPALU_rr<0b0010100, 0b011, "fmaxm.s", FPR32, /*Commutable*/ 1>;
+def FMINM_S: FPALU_rr<0b0010100, 0b010, "fminm.s", FPR32, Commutable=1>;
+def FMAXM_S: FPALU_rr<0b0010100, 0b011, "fmaxm.s", FPR32, Commutable=1>;
}
def FROUND_S : FPUnaryOp_r_frm<0b0100000, 0b00100, FPR32, FPR32, "fround.s">,
@@ -111,8 +111,8 @@ def FLI_D : FPUnaryOp_imm<0b1111001, 0b00001, 0b000, OPC_OP_FP, (outs FPR64:$rd)
Sched<[WriteFLI64]>;
let SchedRW = [WriteFMinMax64, ReadFMinMax64, ReadFMinMax64] in {
-def FMINM_D: FPALU_rr<0b0010101, 0b010, "fminm.d", FPR64, /*Commutable*/ 1>;
-def FMAXM_D: FPALU_rr<0b0010101, 0b011, "fmaxm.d", FPR64, /*Commutable*/ 1>;
+def FMINM_D: FPALU_rr<0b0010101, 0b010, "fminm.d", FPR64, Commutable=1>;
+def FMAXM_D: FPALU_rr<0b0010101, 0b011, "fmaxm.d", FPR64, Commutable=1>;
}
def FROUND_D : FPUnaryOp_r_frm<0b0100001, 0b00100, FPR64, FPR64, "fround.d">,
@@ -152,8 +152,8 @@ def FLI_H : FPUnaryOp_imm<0b1111010, 0b00001, 0b000, OPC_OP_FP, (outs FPR16:$rd)
let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in {
-def FMINM_H: FPALU_rr<0b0010110, 0b010, "fminm.h", FPR16, /*Commutable*/ 1>;
-def FMAXM_H: FPALU_rr<0b0010110, 0b011, "fmaxm.h", FPR16, /*Commutable*/ 1>;
+def FMINM_H: FPALU_rr<0b0010110, 0b010, "fminm.h", FPR16, Commutable=1>;
+def FMAXM_H: FPALU_rr<0b0010110, 0b011, "fmaxm.h", FPR16, Commutable=1>;
}
def FROUND_H : FPUnaryOp_r_frm<0b0100010, 0b00100, FPR16, FPR16, "fround.h">,
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
index 4de2ba127cd2d4..3ea338d9ed20dd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td
@@ -93,11 +93,11 @@ foreach Ext = ZfhExts in {
}
let SchedRW = [WriteFAdd16, ReadFAdd16, ReadFAdd16] in {
- defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", Ext, /*Commutable*/1>;
+ defm FADD_H : FPALU_rr_frm_m<0b0000010, "fadd.h", Ext, Commutable=1>;
defm FSUB_H : FPALU_rr_frm_m<0b0000110, "fsub.h", Ext>;
}
let SchedRW = [WriteFMul16, ReadFMul16, ReadFMul16] in
- defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", Ext, /*Commutable*/1>;
+ defm FMUL_H : FPALU_rr_frm_m<0b0001010, "fmul.h", Ext, Commutable=1>;
let SchedRW = [WriteFDiv16, ReadFDiv16, ReadFDiv16] in
defm FDIV_H : FPALU_rr_frm_m<0b0001110, "fdiv.h", Ext>;
@@ -114,8 +114,8 @@ foreach Ext = ZfhExts in {
}
let SchedRW = [WriteFMinMax16, ReadFMinMax16, ReadFMinMax16] in {
- defm FMIN_H : FPALU_rr_m<0b0010110, 0b000, "fmin.h", Ext, /*Commutable*/1>;
- defm FMAX_H : FPALU_rr_m<0b0010110, 0b001, "fmax.h", Ext, /*Commutable*/1>;
+ defm FMIN_H : FPALU_rr_m<0b0010110, 0b000, "fmin.h", Ext, Commutable=1>;
+ defm FMAX_H : FPALU_rr_m<0b0010110, 0b001, "fmax.h", Ext, Commutable=1>;
}
let IsSignExtendingOpW = 1 in
@@ -159,7 +159,7 @@ def FMV_H_X : FPUnaryOp_r<0b1111010, 0b00000, 0b000, FPR16, GPR, "fmv.h.x">,
foreach Ext = ZfhExts in {
let SchedRW = [WriteFCmp16, ReadFCmp16, ReadFCmp16] in {
- defm FEQ_H : FPCmp_rr_m<0b1010010, 0b010, "feq.h", Ext, /*Commutable*/1>;
+ defm FEQ_H : FPCmp_rr_m<0b1010010, 0b010, "feq.h", Ext, Commutable=1>;
defm FLT_H : FPCmp_rr_m<0b1010010, 0b001, "flt.h", Ext>;
defm FLE_H : FPCmp_rr_m<0b1010010, 0b000, "fle.h", Ext>;
}
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
index 6ab03130ac11a0..920c16c7dbc6be 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
@@ -188,7 +188,7 @@ multiclass VPseudoUnaryV_V {
let VLMul = m.value in {
def "_V_" # m.MX : VPseudoUnaryNoMask<m.vrclass, m.vrclass>;
def "_V_" # m.MX # "_MASK" : VPseudoUnaryMask<m.vrclass, m.vrclass>,
- RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
+ RISCVMaskedPseudo<MaskIdx=2>;
}
}
}
diff --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index cbca9e550974e1..e22c05b30b7faa 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -708,7 +708,7 @@ foreach mx = SchedMxList in {
}
}
foreach mx = SchedMxListF in {
- foreach sew = SchedSEWSet<mx, /*isF*/ 1>.val in {
+ foreach sew = SchedSEWSet<mx, isF=1>.val in {
defvar Cycles = !mul(SiFive7GetDivOrSqrtFactor<sew>.c,
!div(SiFive7GetCyclesOnePerElement<mx, sew>.c, 4));
defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxListF, 1>.c;
diff --git a/llvm/lib/Target/RISCV/RISCVScheduleV.td b/llvm/lib/Target/RISCV/RISCVScheduleV.td
index d823fa70fdd369..676383c5a63656 100644
--- a/llvm/lib/Target/RISCV/RISCVScheduleV.td
+++ b/llvm/lib/Target/RISCV/RISCVScheduleV.td
@@ -170,21 +170,21 @@ multiclass LMULSEWReadAdvance<string name, int val, list<SchedWrite> writes = []
: LMULSEWReadAdvanceImpl<name, val, writes, SchedMxList>;
multiclass LMULSEWSchedWritesWRed<string name>
- : LMULSEWSchedWritesImpl<name, SchedMxListWRed, 0, 1>;
+ : LMULSEWSchedWritesImpl<name, SchedMxListWRed, isWidening=1>;
multiclass LMULSEWWriteResWRed<string name, list<ProcResourceKind> resources>
- : LMULSEWWriteResImpl<name, resources, SchedMxListWRed, 0, 1>;
+ : LMULSEWWriteResImpl<name, resources, SchedMxListWRed, isWidening=1>;
multiclass LMULSEWSchedWritesFWRed<string name>
- : LMULSEWSchedWritesImpl<name, SchedMxListFWRed, 1, 1>;
+ : LMULSEWSchedWritesImpl<name, SchedMxListFWRed, isF=1, isWidening=1>;
multiclass LMULSEWWriteResFWRed<string name, list<ProcResourceKind> resources>
- : LMULSEWWriteResImpl<name, resources, SchedMxListFWRed, 1, 1>;
+ : LMULSEWWriteResImpl<name, resources, SchedMxListFWRed, isF=1, isWidening=1>;
-multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, 1>;
-multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, 1>;
+multiclass LMULSEWSchedWritesF<string name> : LMULSEWSchedWritesImpl<name, SchedMxListF, isF=1>;
+multiclass LMULSEWSchedReadsF<string name> : LMULSEWSchedReadsImpl<name, SchedMxListF, isF=1>;
multiclass LMULSEWWriteResF<string name, list<ProcResourceKind> resources>
- : LMULSEWWriteResImpl<name, resources, SchedMxListF, 1>;
+ : LMULSEWWriteResImpl<name, resources, SchedMxListF, isF=1>;
multiclass LMULSEWReadAdvanceF<string name, int val, list<SchedWrite> writes = []>
- : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, 1>;
+ : LMULSEWReadAdvanceImpl<name, val, writes, SchedMxListF, isF=1>;
multiclass LMULSchedWritesW<string name> : LMULSchedWritesImpl<name, SchedMxListW>;
multiclass LMULSchedReadsW<string name> : LMULSchedReadsImpl<name, SchedMxListW>;
More information about the llvm-commits
mailing list