[PATCH] D155797: [RISCV] Remove Opcode field from RVInst. Assign Inst{6-0} directly. NFC

[Craig Topper via Phabricator via llvm-commits]

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Most places assign Opcode right after assigning every other bit in
Inst. I don't think treating Opcode separately adds much value. It
doesn't hide what bits belong to the opcode since every other bits is
listed.

This makes RVInst consistent with RVInst16 subclasss which already
assign Inst{1-0} directly.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155797

Files:
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrFormatsV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
  llvm/lib/Target/RISCV/RISCVInstrInfoXTHead.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td

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