[PATCH] D155274: [GIsel][AArch64] extend legalization of G_INSERT_VECTOR_ELT

Thu Jul 20 00:48:52 PDT 2023

aemerson accepted this revision.
aemerson added a comment.
This revision is now accepted and ready to land.

You can just add the test case to the existing one in `AArch64/GlobalISel/legalize-insert-vector-elt.mir`

================
Comment at: llvm/test/CodeGen/AArch64/GlobalISel/pr-63826.mir:18-19
+    %0:_(<2 x s16>) = IMPLICIT_DEF
+    %1:_(s16) = IMPLICIT_DEF
+    %2:_(s32) = IMPLICIT_DEF
+    %4:_(<2 x s16>) = G_INSERT_VECTOR_ELT %0(<2 x s16>), %1(s16), %2(s32)
----------------
I prefer to use real values instead of undef for these in case some legalizer combine tries to be smart and elides them in future. For aarch64 you can just use copies from the fpr registers:
```
%1:_(s16) = COPY $h0
%2:_(s16) = COPY $h1
```

Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155274/new/

https://reviews.llvm.org/D155274