[llvm] d76d5c7 - [RISCV] Sink more common code from RVInst/RVInst16 into RVInstCommon. NFC

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-20T00:13:31-07:00
New Revision: d76d5c7d892f06fa42b9ec2ea3e90b6f95cc0e7e

URL: https://github.com/llvm/llvm-project/commit/d76d5c7d892f06fa42b9ec2ea3e90b6f95cc0e7e
DIFF: https://github.com/llvm/llvm-project/commit/d76d5c7d892f06fa42b9ec2ea3e90b6f95cc0e7e.diff

LOG: [RISCV] Sink more common code from RVInst/RVInst16 into RVInstCommon. NFC

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D155787

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVInstrFormats.td
    llvm/lib/Target/RISCV/RISCVInstrFormatsC.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVInstrFormats.td b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
index 470f8940e48e88..022f7d1fcf6c9c 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -156,9 +156,15 @@ def OPC_SYSTEM    : RISCVOpcode<"SYSTEM",    0b1110011>;
 def OPC_OP_P      : RISCVOpcode<"OP_P",      0b1110111>;
 def OPC_CUSTOM_3  : RISCVOpcode<"CUSTOM_3",  0b1111011>;
 
-class RVInstCommon<InstFormat format> : Instruction {
+class RVInstCommon<dag outs, dag ins, string opcodestr, string argstr,
+                   list<dag> pattern, InstFormat format> : Instruction {
   let Namespace = "RISCV";
 
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
+  let AsmString = opcodestr # "\t" # argstr;
+  let Pattern = pattern;
+
   let TSFlags{4-0} = format.Value;
 
   // Defaults
@@ -210,7 +216,7 @@ class RVInstCommon<InstFormat format> : Instruction {
 
 class RVInst<dag outs, dag ins, string opcodestr, string argstr,
              list<dag> pattern, InstFormat format>
-    : RVInstCommon<format> {
+    : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<32> Inst;
   // SoftFail is a field the disassembler can use to provide a way for
   // instructions to not match without killing the whole decode process. It is
@@ -222,11 +228,6 @@ class RVInst<dag outs, dag ins, string opcodestr, string argstr,
   bits<7> Opcode = 0;
 
   let Inst{6-0} = Opcode;
-
-  dag OutOperandList = outs;
-  dag InOperandList = ins;
-  let AsmString = opcodestr # "\t" # argstr;
-  let Pattern = pattern;
 }
 
 // Pseudo instructions

diff  --git a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
index ee3621bb8c8ab2..9575866731225e 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -12,7 +12,7 @@
 
 class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
-    : RVInstCommon<format> {
+    : RVInstCommon<outs, ins, opcodestr, argstr, pattern, format> {
   field bits<16> Inst;
   // SoftFail is a field the disassembler can use to provide a way for
   // instructions to not match without killing the whole decode process. It is
@@ -22,11 +22,6 @@ class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
   let Size = 2;
 
   bits<2> Opcode = 0;
-
-  dag OutOperandList = outs;
-  dag InOperandList = ins;
-  let AsmString = opcodestr # "\t" # argstr;
-  let Pattern = pattern;
 }
 
 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,