[PATCH] D153748: [RISCV] Add support for XCValu extension in CV32E40P

[QIHAN CAI via Phabricator via llvm-commits]

realqhc marked 3 inline comments as done.
realqhc added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:233
+                  Sched<[]>;
+  def CV_SLET   : CVInstAlu_rr<0b0101001, 0b011, (outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2),
+                               "cv.slet", "$rd, $rs1, $rs2">,
----------------
craig.topper wrote:
> I would have expected cv.sle and cv.sleu for these mnemonics. The `t` feels out of place. In the base isa for slt/sltu it's part of "less than". Is the instruction name here "set less equal than" instead "set less than or equal"?
> 
> The vector spec uses "sle" and "sleu"
> 
> Is the spec frozen?
The current naming is copied from PULP RI5CY and it is close to be frozen[1]. 
[1]: https://github.com/openhwgroup/cv32e40p/issues/833


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoXCV.td:260
+                  Sched<[]>;
+  def CV_EXTBZ  : CVInstAlu_r<0b0110011, 0b011, (outs GPR:$rd), (ins GPR:$rs1),
+                              "cv.extbz", "$rd, $rs1">,
----------------
craig.topper wrote:
> I'm surprised this instruction exists. Isn't this `andi rs1, 255`?
I believe this is also a leftover from PULP RI5CY. 


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https://reviews.llvm.org/D153748