[PATCH] D155718: [InstCombine] Remove unneeded isa<PHINode> check in foldOpIntoPhi
Dhruv Chawla via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 19 21:25:26 PDT 2023
0xdc03 updated this revision to Diff 542297.
0xdc03 added a comment.
- Rebase on updated test
- Fix broken test
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D155718/new/
https://reviews.llvm.org/D155718
Files:
llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
llvm/test/Analysis/ValueTracking/known-power-of-two-urem.ll
llvm/test/Transforms/InstCombine/icmp-fold-into-phi.ll
Index: llvm/test/Transforms/InstCombine/icmp-fold-into-phi.ll
===================================================================
--- llvm/test/Transforms/InstCombine/icmp-fold-into-phi.ll
+++ llvm/test/Transforms/InstCombine/icmp-fold-into-phi.ll
@@ -10,14 +10,14 @@
; CHECK-NEXT: i32 1, label [[BB3:%.*]]
; CHECK-NEXT: ]
; CHECK: bb1:
+; CHECK-NEXT: [[TMP0:%.*]] = icmp ugt i32 [[Y]], 1
; CHECK-NEXT: br label [[BB2]]
; CHECK: bb2:
-; CHECK-NEXT: [[PHI1:%.*]] = phi i32 [ 1, [[ENTRY:%.*]] ], [ [[Y]], [[BB1]] ]
+; CHECK-NEXT: [[PHI1:%.*]] = phi i1 [ false, [[ENTRY:%.*]] ], [ [[TMP0]], [[BB1]] ]
; CHECK-NEXT: br label [[BB3]]
; CHECK: bb3:
-; CHECK-NEXT: [[PHI2:%.*]] = phi i32 [ [[PHI1]], [[BB2]] ], [ 0, [[ENTRY]] ]
-; CHECK-NEXT: [[CMP:%.*]] = icmp ugt i32 [[PHI2]], 1
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: [[PHI2:%.*]] = phi i1 [ [[PHI1]], [[BB2]] ], [ false, [[ENTRY]] ]
+; CHECK-NEXT: ret i1 [[PHI2]]
;
entry:
switch i32 %x, label %bb1 [
@@ -71,18 +71,14 @@
; CHECK: cond.end:
; CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr @ObjVal, align 8
; CHECK-NEXT: [[CALL4:%.*]] = tail call zeroext i1 @StrCmp(ptr noundef [[TMP4]], ptr noundef nonnull @.str.3)
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CALL4]], i32 127, i32 126
; CHECK-NEXT: br label [[SW_BB]]
; CHECK: sw.bb:
-; CHECK-NEXT: [[COND2:%.*]] = phi i32 [ [[COND]], [[COND_END]] ], [ 128, [[COND_FALSE3]] ]
; CHECK-NEXT: [[CALL5:%.*]] = tail call zeroext i1 @CheckCond()
; CHECK-NEXT: [[NOT_CALL5:%.*]] = xor i1 [[CALL5]], true
; CHECK-NEXT: br label [[SW_EPILOG]]
; CHECK: sw.epilog:
-; CHECK-NEXT: [[COND3:%.*]] = phi i32 [ [[COND2]], [[SW_BB]] ], [ 134, [[COND_FALSE2]] ], [ 2, [[COND_FALSE]] ], [ 1, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[TAGERROR_0:%.*]] = phi i1 [ [[NOT_CALL5]], [[SW_BB]] ], [ false, [[COND_FALSE2]] ], [ false, [[COND_FALSE]] ], [ false, [[ENTRY]] ]
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[COND3]], 2
-; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[CMP]], [[TAGERROR_0]]
+; CHECK-NEXT: [[TAGERROR_0:%.*]] = phi i1 [ [[NOT_CALL5]], [[SW_BB]] ], [ false, [[COND_FALSE2]] ], [ false, [[COND_FALSE]] ], [ false, [[ENTRY:%.*]] ]
+; CHECK-NEXT: [[BRMERGE:%.*]] = or i1 [[CALL]], [[TAGERROR_0]]
; CHECK-NEXT: [[RETVAL2_VAL:%.*]] = load i32, ptr @RetVal2, align 4
; CHECK-NEXT: [[RETVAL1_VAL:%.*]] = load i32, ptr @RetVal1, align 4
; CHECK-NEXT: [[RETVAL_0:%.*]] = select i1 [[BRMERGE]], i32 [[RETVAL2_VAL]], i32 [[RETVAL1_VAL]]
@@ -152,15 +148,11 @@
; CHECK: cond.end:
; CHECK-NEXT: [[TMP4:%.*]] = load ptr, ptr @ObjVal, align 8
; CHECK-NEXT: [[CALL4:%.*]] = tail call zeroext i1 @StrCmp(ptr noundef [[TMP4]], ptr noundef nonnull @.str.3)
-; CHECK-NEXT: [[COND:%.*]] = select i1 [[CALL4]], i32 127, i32 126
; CHECK-NEXT: br label [[SW_BB]]
; CHECK: sw.bb:
-; CHECK-NEXT: [[COND2:%.*]] = phi i32 [ [[COND]], [[COND_END]] ], [ 128, [[COND_FALSE3]] ]
; CHECK-NEXT: br label [[SW_EPILOG]]
; CHECK: sw.epilog:
-; CHECK-NEXT: [[COND3:%.*]] = phi i32 [ [[COND2]], [[SW_BB]] ], [ 134, [[COND_FALSE2]] ], [ 2, [[COND_FALSE]] ], [ 1, [[ENTRY:%.*]] ]
-; CHECK-NEXT: [[CMP:%.*]] = icmp ult i32 [[COND3]], 2
-; CHECK-NEXT: ret i1 [[CMP]]
+; CHECK-NEXT: ret i1 [[CALL]]
;
entry:
%0 = load i32, ptr @ObjTag, align 4
Index: llvm/test/Analysis/ValueTracking/known-power-of-two-urem.ll
===================================================================
--- llvm/test/Analysis/ValueTracking/known-power-of-two-urem.ll
+++ llvm/test/Analysis/ValueTracking/known-power-of-two-urem.ll
@@ -15,12 +15,11 @@
; CHECK: cond.true.false:
; CHECK-NEXT: br label [[COND_TRUE_END]]
; CHECK: cond.true.end:
-; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ 2, [[COND_TRUE_TRUE]] ], [ 4, [[COND_TRUE_FALSE]] ]
+; CHECK-NEXT: [[PHI:%.*]] = phi i64 [ 1, [[COND_TRUE_TRUE]] ], [ 3, [[COND_TRUE_FALSE]] ]
; CHECK-NEXT: br label [[COND_END]]
; CHECK: cond.end:
-; CHECK-NEXT: [[PHI1:%.*]] = phi i64 [ 4096, [[ENTRY:%.*]] ], [ [[PHI]], [[COND_TRUE_END]] ]
-; CHECK-NEXT: [[TMP0:%.*]] = add nsw i64 [[PHI1]], -1
-; CHECK-NEXT: [[UREM:%.*]] = and i64 [[TMP0]], [[SIZE:%.*]]
+; CHECK-NEXT: [[PHI1:%.*]] = phi i64 [ 4095, [[ENTRY:%.*]] ], [ [[PHI]], [[COND_TRUE_END]] ]
+; CHECK-NEXT: [[UREM:%.*]] = and i64 [[PHI1]], [[SIZE:%.*]]
; CHECK-NEXT: ret i64 [[UREM]]
;
entry:
Index: llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
===================================================================
--- llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
+++ llvm/lib/Transforms/InstCombine/InstructionCombining.cpp
@@ -1297,7 +1297,6 @@
continue;
}
- if (isa<PHINode>(InVal)) return nullptr; // Itself a phi.
if (NonSimplifiedBB) return nullptr; // More than one non-simplified value.
NonSimplifiedBB = InBB;
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