[PATCH] D155772: [RISCV][GlobalISel] Legalize bitshift instructions for narrow types

[Nitin John Raj via Phabricator via llvm-commits]

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Legalize G_SHL, G_ASHR and G_LSHR for types narrower and upto XLen (i8,
i16 and i32 for rv32 and additionally i64 for rv64). This requires
adding some rules to handle G_ANYEXT, G_ZEXT and G_SEXT.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155772

Files:
  llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-ashr.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-lshr.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-shl.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-ashr.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-lshr.mir
  llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-shl.mir

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