[llvm] ccffc27 - [AArch64][GlobalISel] Widen (<2 x s16> = G_BUILD_VECTOR) to <2 x s32>.
Amara Emerson via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 19 16:51:12 PDT 2023
Author: Amara Emerson
Date: 2023-07-19T16:50:54-07:00
New Revision: ccffc2705054c24a5768b59fbb96c3044ff1a8d4
URL: https://github.com/llvm/llvm-project/commit/ccffc2705054c24a5768b59fbb96c3044ff1a8d4
DIFF: https://github.com/llvm/llvm-project/commit/ccffc2705054c24a5768b59fbb96c3044ff1a8d4.diff
LOG: [AArch64][GlobalISel] Widen (<2 x s16> = G_BUILD_VECTOR) to <2 x s32>.
We don't support this as a argument or return type, it's always promoted to <2 x s32>.
Performing the widening prevents us from having selection failures due to unsupported
extends.
Fixes https://github.com/llvm/llvm-project/issues/58274
Added:
Modified:
llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
Removed:
################################################################################
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
index 356bd621ff3788..49ce79cefffda8 100644
--- a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
+++ b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -707,7 +707,6 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
getActionDefinitionsBuilder(G_BUILD_VECTOR)
.legalFor({{v8s8, s8},
{v16s8, s8},
- {v2s16, s16},
{v4s16, s16},
{v8s16, s16},
{v2s32, s32},
@@ -717,6 +716,9 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
.clampNumElements(0, v4s32, v4s32)
.clampNumElements(0, v2s64, v2s64)
.minScalarOrElt(0, s8)
+ .minScalarOrEltIf(
+ [=](const LegalityQuery &Query) { return Query.Types[0] == v2s16; },
+ 0, s32)
.minScalarSameAs(1, 0);
getActionDefinitionsBuilder(G_BUILD_VECTOR_TRUNC).lower();
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
index 531794b140429e..b64bcd4426b07e 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-build-vector.mir
@@ -7,7 +7,9 @@ body: |
bb.0:
liveins: $w0, $w1, $w2, $w3
; CHECK-LABEL: name: legal_v4s32
- ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
+ ; CHECK: liveins: $w0, $w1, $w2, $w3
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s32) = COPY $w0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[COPY2:%[0-9]+]]:_(s32) = COPY $w2
; CHECK-NEXT: [[COPY3:%[0-9]+]]:_(s32) = COPY $w3
@@ -28,7 +30,9 @@ body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: legal_v2s64
- ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
+ ; CHECK: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s64) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s64>) = G_BUILD_VECTOR [[COPY]](s64), [[COPY1]](s64)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<2 x s64>)
@@ -45,7 +49,9 @@ body: |
bb.0:
liveins: $x0, $x1
; CHECK-LABEL: name: legal_v2p0
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(p0) = COPY $x1
; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x p0>) = G_BUILD_VECTOR [[COPY]](p0), [[COPY1]](p0)
; CHECK-NEXT: $q0 = COPY [[BUILD_VECTOR]](<2 x p0>)
@@ -105,3 +111,25 @@ body: |
$q0 = COPY %w(<16 x s8>)
RET_ReallyLR
...
+---
+name: widen_v2s16
+body: |
+ bb.0:
+ liveins: $x0, $x1
+ ; CHECK-LABEL: name: widen_v2s16
+ ; CHECK: liveins: $x0, $x1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(s16) = COPY $h0
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s16) = COPY $h1
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY]](s16)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[COPY1]](s16)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
+ ; CHECK-NEXT: $d0 = COPY [[BUILD_VECTOR]](<2 x s32>)
+ ; CHECK-NEXT: RET_ReallyLR
+ %0:_(s16) = COPY $h0
+ %1:_(s16) = COPY $h1
+ %2:_(<2 x s16>) = G_BUILD_VECTOR %0(s16), %1(s16)
+ %ext:_(<2 x s32>) = G_ANYEXT %2(<2 x s16>)
+ $d0 = COPY %ext(<2 x s32>)
+ RET_ReallyLR
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
index f63b547b6d08f9..1040a5d6ff4d99 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-load-store.mir
@@ -7,7 +7,9 @@ body: |
liveins: $x0
; CHECK-LABEL: name: test_load
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: liveins: $x0
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[LOAD:%[0-9]+]]:_(s8) = G_LOAD [[COPY]](p0) :: (load (s8))
; CHECK-NEXT: [[ASSERT_ZEXT:%[0-9]+]]:_(s8) = G_ASSERT_ZEXT [[LOAD]], 1
; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[ASSERT_ZEXT]](s8)
@@ -62,7 +64,9 @@ body: |
liveins: $x0, $w1
; CHECK-LABEL: name: test_store
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: liveins: $x0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: [[C:%[0-9]+]]:_(s32) = G_CONSTANT i32 1
; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY1]], [[C]]
@@ -518,7 +522,9 @@ body: |
liveins: $x0, $w1
; CHECK-LABEL: name: test_trunc_store
- ; CHECK: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
+ ; CHECK: liveins: $x0, $w1
+ ; CHECK-NEXT: {{ $}}
+ ; CHECK-NEXT: [[COPY:%[0-9]+]]:_(p0) = COPY $x0
; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $w1
; CHECK-NEXT: %val64:_(s64) = COPY $x2
; CHECK-NEXT: G_STORE [[COPY1]](s32), [[COPY]](p0) :: (store (s8))
@@ -599,8 +605,11 @@ body: |
; CHECK-NEXT: [[C:%[0-9]+]]:_(s64) = G_CONSTANT i64 2
; CHECK-NEXT: [[PTR_ADD:%[0-9]+]]:_(p0) = G_PTR_ADD [[COPY]], [[C]](s64)
; CHECK-NEXT: [[LOAD1:%[0-9]+]]:_(s16) = G_LOAD [[PTR_ADD]](p0) :: (load (s16) from unknown-address + 2)
- ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s16>) = G_BUILD_VECTOR [[LOAD]](s16), [[LOAD1]](s16)
- ; CHECK-NEXT: $s0 = COPY [[BUILD_VECTOR]](<2 x s16>)
+ ; CHECK-NEXT: [[ANYEXT:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD]](s16)
+ ; CHECK-NEXT: [[ANYEXT1:%[0-9]+]]:_(s32) = G_ANYEXT [[LOAD1]](s16)
+ ; CHECK-NEXT: [[BUILD_VECTOR:%[0-9]+]]:_(<2 x s32>) = G_BUILD_VECTOR [[ANYEXT]](s32), [[ANYEXT1]](s32)
+ ; CHECK-NEXT: [[TRUNC:%[0-9]+]]:_(<2 x s16>) = G_TRUNC [[BUILD_VECTOR]](<2 x s32>)
+ ; CHECK-NEXT: $s0 = COPY [[TRUNC]](<2 x s16>)
; CHECK-NEXT: RET_ReallyLR
%0:_(p0) = COPY $x0
%1(<2 x s16>) = G_LOAD %0(p0) :: (load (<2 x s16>))
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir b/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
index 0c0f9ae896c7d3..459b3387cd898f 100644
--- a/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
+++ b/llvm/test/CodeGen/AArch64/GlobalISel/select-unmerge.mir
@@ -109,14 +109,9 @@ body: |
; CHECK-NEXT: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
; CHECK-NEXT: [[COPY1:%[0-9]+]]:fpr16 = COPY [[INSERT_SUBREG]].hsub
; CHECK-NEXT: [[DUPi16_:%[0-9]+]]:fpr16 = DUPi16 [[INSERT_SUBREG]], 1
- ; CHECK-NEXT: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY1]], %subreg.hsub
- ; CHECK-NEXT: [[DEF2:%[0-9]+]]:fpr128 = IMPLICIT_DEF
- ; CHECK-NEXT: [[INSERT_SUBREG2:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF2]], [[DUPi16_]], %subreg.hsub
- ; CHECK-NEXT: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[INSERT_SUBREG1]], 1, [[INSERT_SUBREG2]], 0
- ; CHECK-NEXT: [[COPY2:%[0-9]+]]:fpr32 = COPY [[INSvi16lane]].ssub
- ; CHECK-NEXT: $s0 = COPY [[COPY2]]
- ; CHECK-NEXT: RET_ReallyLR implicit $s0
+ ; CHECK-NEXT: $h0 = COPY [[COPY1]]
+ ; CHECK-NEXT: $h1 = COPY [[DUPi16_]]
+ ; CHECK-NEXT: RET_ReallyLR implicit $h0, implicit $h1
%0:fpr(<2 x s16>) = COPY $s0
; Since 2 * 16 != 128, we need to widen using implicit defs.
@@ -124,11 +119,10 @@ body: |
; expects a lane > 0.
%2:fpr(s16), %3:fpr(s16) = G_UNMERGE_VALUES %0(<2 x s16>)
- %1:fpr(<2 x s16>) = G_BUILD_VECTOR %2(s16), %3(s16)
+ $h0 = COPY %2(s16)
+ $h1 = COPY %3(s16)
- $s0 = COPY %1(<2 x s16>)
-
- RET_ReallyLR implicit $s0
+ RET_ReallyLR implicit $h0, implicit $h1
...
---
name: test_v4s16_unmerge
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