[PATCH] D155439: [RISCV] Add SDNode patterns for vrol.[vv,vx] and vror.[vv,vx,vi]

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:455
+def ImmSubFrom64 : SDNodeXForm<imm, [{
+  return CurDAG->getTargetConstant(64 - N->getZExtValue(), SDLoc(N),
+                                   N->getValueType(0));
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Out of an abundance of paranoia can you mask this with 0x3f. The original match was for a uimm which would allow 0-63. 0 would be a noop roate. I don't trust that the 0 won't show up since we are on target nodes and don't have DAG combines to clean it up if the 0 appears late. 64 - 0 would be 64 which would be an invalid value for the assembly. Masking 64 to 0 would prevent that from being a problem.


Repository:
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CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155439/new/

https://reviews.llvm.org/D155439