[PATCH] D154083: [AMDGPU] Rematerialize scalar loads

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added a comment.

In D154083#4493643 <https://reviews.llvm.org/D154083#4493643>, @piotr wrote:

> In D154083#4490691 <https://reviews.llvm.org/D154083#4490691>, @arsenm wrote:
>
>> Could really use a MIR test that shows this. Also would be nice to have some evil cases, where the result register is tied to the input pointer register
>
> This patch is now based on a test update (https://reviews.llvm.org/D154816), where I am also adding a new test that exercises the shrinking - test_remat_s_load_dword_immx16_subreg.
>
> Can you describe the evil case(s) in more detail? Do you mean S_LOAD_DWORDX16_IMM with tied-def, or something else?

Yes. I don't think subregisters with tied operands are particularly well defined, but I was thinking something like %0:sreg_256 = S_LOAD_DWORDX16 %0.sub0_sub1


Repository:
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  https://reviews.llvm.org/D154083/new/

https://reviews.llvm.org/D154083