[PATCH] D155744: [RISCV] Introduce a common tablegen base class for RVInst and RVInst16.

[Craig Topper via Phabricator via llvm-commits]

craig.topper created this revision.
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This gives us a common place to put the TSFlags and the Namespace.

Removes TSFlags declaration duplication for D155690 <https://reviews.llvm.org/D155690>.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155744

Files:
  llvm/lib/Target/RISCV/RISCVInstrFormats.td
  llvm/lib/Target/RISCV/RISCVInstrFormatsC.td


Index: llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
+++ llvm/lib/Target/RISCV/RISCVInstrFormatsC.td
@@ -12,7 +12,7 @@
 
 class RVInst16<dag outs, dag ins, string opcodestr, string argstr,
                list<dag> pattern, InstFormat format>
-    : Instruction {
+    : RVInstCommon<format> {
   field bits<16> Inst;
   // SoftFail is a field the disassembler can use to provide a way for
   // instructions to not match without killing the whole decode process. It is
@@ -23,14 +23,10 @@
 
   bits<2> Opcode = 0;
 
-  let Namespace = "RISCV";
-
   dag OutOperandList = outs;
   dag InOperandList = ins;
   let AsmString = opcodestr # "\t" # argstr;
   let Pattern = pattern;
-
-  let TSFlags{4-0} = format.Value;
 }
 
 class RVInst16CR<bits<4> funct4, bits<2> opcode, dag outs, dag ins,
Index: llvm/lib/Target/RISCV/RISCVInstrFormats.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrFormats.td
+++ llvm/lib/Target/RISCV/RISCVInstrFormats.td
@@ -156,28 +156,9 @@
 def OPC_OP_P      : RISCVOpcode<"OP_P",      0b1110111>;
 def OPC_CUSTOM_3  : RISCVOpcode<"CUSTOM_3",  0b1111011>;
 
-class RVInst<dag outs, dag ins, string opcodestr, string argstr,
-             list<dag> pattern, InstFormat format>
-    : Instruction {
-  field bits<32> Inst;
-  // SoftFail is a field the disassembler can use to provide a way for
-  // instructions to not match without killing the whole decode process. It is
-  // mainly used for ARM, but Tablegen expects this field to exist or it fails
-  // to build the decode table.
-  field bits<32> SoftFail = 0;
-  let Size = 4;
-
-  bits<7> Opcode = 0;
-
-  let Inst{6-0} = Opcode;
-
+class RVInstCommon<InstFormat format> : Instruction {
   let Namespace = "RISCV";
 
-  dag OutOperandList = outs;
-  dag InOperandList = ins;
-  let AsmString = opcodestr # "\t" # argstr;
-  let Pattern = pattern;
-
   let TSFlags{4-0} = format.Value;
 
   // Defaults
@@ -227,6 +208,27 @@
   let TSFlags{20} =  UsesVXRM;
 }
 
+class RVInst<dag outs, dag ins, string opcodestr, string argstr,
+             list<dag> pattern, InstFormat format>
+    : RVInstCommon<format> {
+  field bits<32> Inst;
+  // SoftFail is a field the disassembler can use to provide a way for
+  // instructions to not match without killing the whole decode process. It is
+  // mainly used for ARM, but Tablegen expects this field to exist or it fails
+  // to build the decode table.
+  field bits<32> SoftFail = 0;
+  let Size = 4;
+
+  bits<7> Opcode = 0;
+
+  let Inst{6-0} = Opcode;
+
+  dag OutOperandList = outs;
+  dag InOperandList = ins;
+  let AsmString = opcodestr # "\t" # argstr;
+  let Pattern = pattern;
+}
+
 // Pseudo instructions
 class Pseudo<dag outs, dag ins, list<dag> pattern, string opcodestr = "", string argstr = "">
     : RVInst<outs, ins, opcodestr, argstr, pattern, InstFormatPseudo> {


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