[PATCH] D155690: [RISCV] Mask instructions in Zkt as constant-time

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfo.td:689
 
+let IsConstantTime = 1 in {
 def ANDI  : ALU_ri<0b111, "andi">;
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Can we move this scope start above ADDI? Then we don't need to mention it 3 other times before this.


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Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZb.td:335
 
 let Predicates = [HasStdExtZbbOrZbkb, IsRV64], IsSignExtendingOpW = 1 in {
 def ROLW  : ALUW_rr<0b0110000, 0b001, "rolw">,
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Are ROLW/RORW not in the constant time list? Surely that's a miss in the table in the spec since it says "The Zbkb, Zbkx and Zbkx extensions are included in their entirety."


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155690/new/

https://reviews.llvm.org/D155690