[llvm] 0f277ab - [RISCV] Fold vmerge into its ops with smaller VL if known
Luke Lau via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 19 09:24:50 PDT 2023
Author: Luke Lau
Date: 2023-07-19T17:24:40+01:00
New Revision: 0f277ab3616a16748303c673f1b7c279d5d238d3
URL: https://github.com/llvm/llvm-project/commit/0f277ab3616a16748303c673f1b7c279d5d238d3
DIFF: https://github.com/llvm/llvm-project/commit/0f277ab3616a16748303c673f1b7c279d5d238d3.diff
LOG: [RISCV] Fold vmerge into its ops with smaller VL if known
Currently when folding vmerge into its operands, we stop if the VLs aren't
identical. However since the body of (vmerge (vop)) is the intersection of
vmerge and vop's bodies, we can use the smaller of the two VLs if we know it
ahead of time. This patch relaxes the constraint on VL if they are both
constants, or if either of them are VLMAX.
Reviewed By: reames
Differential Revision: https://reviews.llvm.org/D155071
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
index f7b37eda8bfaac..054ed96c050742 100644
--- a/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp
@@ -3328,10 +3328,24 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
True.getNumOperands() - HasVecPolicyOp - HasChainOp - HasGlueOp - 2;
SDValue TrueVL = True.getOperand(TrueVLIndex);
- // We need the VLs to be the same. But if True has a VL of VLMAX then we can
- // go ahead and use N's VL because we know it will be smaller, so any tail
- // elements in the result will be from Merge.
- if (TrueVL != VL && !isAllOnesConstant(TrueVL))
+ auto GetMinVL = [](SDValue LHS, SDValue RHS) {
+ if (LHS == RHS)
+ return LHS;
+ if (isAllOnesConstant(LHS))
+ return RHS;
+ if (isAllOnesConstant(RHS))
+ return LHS;
+ auto *CLHS = dyn_cast<ConstantSDNode>(LHS);
+ auto *CRHS = dyn_cast<ConstantSDNode>(RHS);
+ if (!CLHS || !CRHS)
+ return SDValue();
+ return CLHS->getZExtValue() <= CRHS->getZExtValue() ? LHS : RHS;
+ };
+
+ // Because N and True must have the same merge operand (or True's operand is
+ // implicit_def), the "effective" body is the minimum of their VLs.
+ VL = GetMinVL(TrueVL, VL);
+ if (!VL)
return false;
// If we end up changing the VL or mask of True, then we need to make sure it
diff --git a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
index 92db0a9e545a9e..64e09cdace4205 100644
--- a/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/fixed-vectors-vselect.ll
@@ -7,31 +7,29 @@ define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV32-NEXT: lbu a2, 0(a2)
-; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: vle32.v v10, (a1)
-; RV32-NEXT: andi a0, a2, 1
+; RV32-NEXT: vle32.v v8, (a1)
+; RV32-NEXT: andi a1, a2, 1
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-NEXT: vslide1down.vx v12, v8, a0
-; RV32-NEXT: slli a0, a2, 30
-; RV32-NEXT: srli a0, a0, 31
-; RV32-NEXT: vslide1down.vx v12, v12, a0
-; RV32-NEXT: slli a0, a2, 29
-; RV32-NEXT: srli a0, a0, 31
-; RV32-NEXT: vslide1down.vx v12, v12, a0
-; RV32-NEXT: slli a0, a2, 28
-; RV32-NEXT: srli a0, a0, 31
-; RV32-NEXT: vslide1down.vx v12, v12, a0
-; RV32-NEXT: slli a0, a2, 27
-; RV32-NEXT: srli a0, a0, 31
-; RV32-NEXT: vslide1down.vx v12, v12, a0
+; RV32-NEXT: vslide1down.vx v10, v8, a1
+; RV32-NEXT: slli a1, a2, 30
+; RV32-NEXT: srli a1, a1, 31
+; RV32-NEXT: vslide1down.vx v10, v10, a1
+; RV32-NEXT: slli a1, a2, 29
+; RV32-NEXT: srli a1, a1, 31
+; RV32-NEXT: vslide1down.vx v10, v10, a1
+; RV32-NEXT: slli a1, a2, 28
+; RV32-NEXT: srli a1, a1, 31
+; RV32-NEXT: vslide1down.vx v10, v10, a1
+; RV32-NEXT: slli a1, a2, 27
+; RV32-NEXT: srli a1, a1, 31
+; RV32-NEXT: vslide1down.vx v10, v10, a1
; RV32-NEXT: srli a2, a2, 5
-; RV32-NEXT: vslide1down.vx v12, v12, a2
-; RV32-NEXT: vslidedown.vi v12, v12, 2
-; RV32-NEXT: vand.vi v12, v12, 1
-; RV32-NEXT: vmsne.vi v0, v12, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v10, v8, v0
-; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma
+; RV32-NEXT: vslide1down.vx v10, v10, a2
+; RV32-NEXT: vslidedown.vi v10, v10, 2
+; RV32-NEXT: vand.vi v10, v10, 1
+; RV32-NEXT: vmsne.vi v0, v10, 0
+; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, mu
+; RV32-NEXT: vle32.v v8, (a0), v0.t
; RV32-NEXT: vse32.v v8, (a3)
; RV32-NEXT: ret
;
@@ -39,31 +37,29 @@ define void @vselect_vv_v6i32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV64-NEXT: lbu a2, 0(a2)
-; RV64-NEXT: vle32.v v8, (a0)
-; RV64-NEXT: vle32.v v10, (a1)
-; RV64-NEXT: andi a0, a2, 1
+; RV64-NEXT: vle32.v v8, (a1)
+; RV64-NEXT: andi a1, a2, 1
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; RV64-NEXT: vslide1down.vx v12, v8, a0
-; RV64-NEXT: slli a0, a2, 62
-; RV64-NEXT: srli a0, a0, 63
-; RV64-NEXT: vslide1down.vx v12, v12, a0
-; RV64-NEXT: slli a0, a2, 61
-; RV64-NEXT: srli a0, a0, 63
-; RV64-NEXT: vslide1down.vx v12, v12, a0
-; RV64-NEXT: slli a0, a2, 60
-; RV64-NEXT: srli a0, a0, 63
-; RV64-NEXT: vslide1down.vx v12, v12, a0
-; RV64-NEXT: slli a0, a2, 59
-; RV64-NEXT: srli a0, a0, 63
-; RV64-NEXT: vslide1down.vx v12, v12, a0
+; RV64-NEXT: vslide1down.vx v10, v8, a1
+; RV64-NEXT: slli a1, a2, 62
+; RV64-NEXT: srli a1, a1, 63
+; RV64-NEXT: vslide1down.vx v10, v10, a1
+; RV64-NEXT: slli a1, a2, 61
+; RV64-NEXT: srli a1, a1, 63
+; RV64-NEXT: vslide1down.vx v10, v10, a1
+; RV64-NEXT: slli a1, a2, 60
+; RV64-NEXT: srli a1, a1, 63
+; RV64-NEXT: vslide1down.vx v10, v10, a1
+; RV64-NEXT: slli a1, a2, 59
+; RV64-NEXT: srli a1, a1, 63
+; RV64-NEXT: vslide1down.vx v10, v10, a1
; RV64-NEXT: srli a2, a2, 5
-; RV64-NEXT: vslide1down.vx v12, v12, a2
-; RV64-NEXT: vslidedown.vi v12, v12, 2
-; RV64-NEXT: vand.vi v12, v12, 1
-; RV64-NEXT: vmsne.vi v0, v12, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
-; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma
+; RV64-NEXT: vslide1down.vx v10, v10, a2
+; RV64-NEXT: vslidedown.vi v10, v10, 2
+; RV64-NEXT: vand.vi v10, v10, 1
+; RV64-NEXT: vmsne.vi v0, v10, 0
+; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, mu
+; RV64-NEXT: vle32.v v8, (a0), v0.t
; RV64-NEXT: vse32.v v8, (a3)
; RV64-NEXT: ret
%va = load <6 x i32>, ptr %a
@@ -222,31 +218,29 @@ define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV32: # %bb.0:
; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV32-NEXT: lbu a2, 0(a2)
-; RV32-NEXT: vle32.v v8, (a0)
-; RV32-NEXT: vle32.v v10, (a1)
-; RV32-NEXT: andi a0, a2, 1
+; RV32-NEXT: vle32.v v8, (a1)
+; RV32-NEXT: andi a1, a2, 1
; RV32-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; RV32-NEXT: vslide1down.vx v12, v8, a0
-; RV32-NEXT: slli a0, a2, 30
-; RV32-NEXT: srli a0, a0, 31
-; RV32-NEXT: vslide1down.vx v12, v12, a0
-; RV32-NEXT: slli a0, a2, 29
-; RV32-NEXT: srli a0, a0, 31
-; RV32-NEXT: vslide1down.vx v12, v12, a0
-; RV32-NEXT: slli a0, a2, 28
-; RV32-NEXT: srli a0, a0, 31
-; RV32-NEXT: vslide1down.vx v12, v12, a0
-; RV32-NEXT: slli a0, a2, 27
-; RV32-NEXT: srli a0, a0, 31
-; RV32-NEXT: vslide1down.vx v12, v12, a0
+; RV32-NEXT: vslide1down.vx v10, v8, a1
+; RV32-NEXT: slli a1, a2, 30
+; RV32-NEXT: srli a1, a1, 31
+; RV32-NEXT: vslide1down.vx v10, v10, a1
+; RV32-NEXT: slli a1, a2, 29
+; RV32-NEXT: srli a1, a1, 31
+; RV32-NEXT: vslide1down.vx v10, v10, a1
+; RV32-NEXT: slli a1, a2, 28
+; RV32-NEXT: srli a1, a1, 31
+; RV32-NEXT: vslide1down.vx v10, v10, a1
+; RV32-NEXT: slli a1, a2, 27
+; RV32-NEXT: srli a1, a1, 31
+; RV32-NEXT: vslide1down.vx v10, v10, a1
; RV32-NEXT: srli a2, a2, 5
-; RV32-NEXT: vslide1down.vx v12, v12, a2
-; RV32-NEXT: vslidedown.vi v12, v12, 2
-; RV32-NEXT: vand.vi v12, v12, 1
-; RV32-NEXT: vmsne.vi v0, v12, 0
-; RV32-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV32-NEXT: vmerge.vvm v8, v10, v8, v0
-; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, ma
+; RV32-NEXT: vslide1down.vx v10, v10, a2
+; RV32-NEXT: vslidedown.vi v10, v10, 2
+; RV32-NEXT: vand.vi v10, v10, 1
+; RV32-NEXT: vmsne.vi v0, v10, 0
+; RV32-NEXT: vsetivli zero, 6, e32, m2, ta, mu
+; RV32-NEXT: vle32.v v8, (a0), v0.t
; RV32-NEXT: vse32.v v8, (a3)
; RV32-NEXT: ret
;
@@ -254,31 +248,29 @@ define void @vselect_vv_v6f32(ptr %a, ptr %b, ptr %cc, ptr %z) {
; RV64: # %bb.0:
; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma
; RV64-NEXT: lbu a2, 0(a2)
-; RV64-NEXT: vle32.v v8, (a0)
-; RV64-NEXT: vle32.v v10, (a1)
-; RV64-NEXT: andi a0, a2, 1
+; RV64-NEXT: vle32.v v8, (a1)
+; RV64-NEXT: andi a1, a2, 1
; RV64-NEXT: vsetivli zero, 8, e8, mf2, ta, ma
-; RV64-NEXT: vslide1down.vx v12, v8, a0
-; RV64-NEXT: slli a0, a2, 62
-; RV64-NEXT: srli a0, a0, 63
-; RV64-NEXT: vslide1down.vx v12, v12, a0
-; RV64-NEXT: slli a0, a2, 61
-; RV64-NEXT: srli a0, a0, 63
-; RV64-NEXT: vslide1down.vx v12, v12, a0
-; RV64-NEXT: slli a0, a2, 60
-; RV64-NEXT: srli a0, a0, 63
-; RV64-NEXT: vslide1down.vx v12, v12, a0
-; RV64-NEXT: slli a0, a2, 59
-; RV64-NEXT: srli a0, a0, 63
-; RV64-NEXT: vslide1down.vx v12, v12, a0
+; RV64-NEXT: vslide1down.vx v10, v8, a1
+; RV64-NEXT: slli a1, a2, 62
+; RV64-NEXT: srli a1, a1, 63
+; RV64-NEXT: vslide1down.vx v10, v10, a1
+; RV64-NEXT: slli a1, a2, 61
+; RV64-NEXT: srli a1, a1, 63
+; RV64-NEXT: vslide1down.vx v10, v10, a1
+; RV64-NEXT: slli a1, a2, 60
+; RV64-NEXT: srli a1, a1, 63
+; RV64-NEXT: vslide1down.vx v10, v10, a1
+; RV64-NEXT: slli a1, a2, 59
+; RV64-NEXT: srli a1, a1, 63
+; RV64-NEXT: vslide1down.vx v10, v10, a1
; RV64-NEXT: srli a2, a2, 5
-; RV64-NEXT: vslide1down.vx v12, v12, a2
-; RV64-NEXT: vslidedown.vi v12, v12, 2
-; RV64-NEXT: vand.vi v12, v12, 1
-; RV64-NEXT: vmsne.vi v0, v12, 0
-; RV64-NEXT: vsetvli zero, zero, e32, m2, ta, ma
-; RV64-NEXT: vmerge.vvm v8, v10, v8, v0
-; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, ma
+; RV64-NEXT: vslide1down.vx v10, v10, a2
+; RV64-NEXT: vslidedown.vi v10, v10, 2
+; RV64-NEXT: vand.vi v10, v10, 1
+; RV64-NEXT: vmsne.vi v0, v10, 0
+; RV64-NEXT: vsetivli zero, 6, e32, m2, ta, mu
+; RV64-NEXT: vle32.v v8, (a0), v0.t
; RV64-NEXT: vse32.v v8, (a3)
; RV64-NEXT: ret
%va = load <6 x float>, ptr %a
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
index 2eaeefb1aa41ca..aef7ffbf5a8930 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-masked-vops.ll
@@ -155,11 +155,8 @@ define <vscale x 2 x i32> @vpmerge_vslide1down(<vscale x 2 x i32> %passthru, <vs
define <vscale x 2 x i32> @vmerge_smaller_vl_same_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: vmerge_smaller_vl_same_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, mu
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vadd.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT: vmv.v.v v8, v11
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 3, i64 0)
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
@@ -173,10 +170,7 @@ define <vscale x 2 x i32> @vmerge_larger_vl_same_passthru(<vscale x 2 x i32> %pa
; CHECK-LABEL: vmerge_larger_vl_same_passthru:
; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vadd.vv v11, v9, v10, v0.t
-; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; CHECK-NEXT: vmv.v.v v8, v11
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 2, i64 0)
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
@@ -223,10 +217,8 @@ define <vscale x 2 x i32> @vmerge_larger_vl_
diff erent_passthru(<vscale x 2 x i32
define <vscale x 2 x i32> @vmerge_smaller_vl_poison_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: vmerge_smaller_vl_poison_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma
-; CHECK-NEXT: vadd.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT: vmv.v.v v8, v9
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 3, i64 0)
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
@@ -239,10 +231,8 @@ define <vscale x 2 x i32> @vmerge_smaller_vl_poison_passthru(<vscale x 2 x i32>
define <vscale x 2 x i32> @vmerge_larger_vl_poison_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: vmerge_larger_vl_poison_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vadd.vv v9, v9, v10, v0.t
-; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; CHECK-NEXT: vmv.v.v v8, v9
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.mask.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m, i64 2, i64 0)
%splat = insertelement <vscale x 2 x i1> poison, i1 -1, i32 0
diff --git a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
index bf70f42c352b87..7620ba53107203 100644
--- a/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
+++ b/llvm/test/CodeGen/RISCV/rvv/rvv-peephole-vmerge-vops.ll
@@ -991,11 +991,8 @@ declare <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32>
define <vscale x 2 x i32> @vmerge_smaller_vl_same_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: vmerge_smaller_vl_same_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 4, e32, m1, tu, ma
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vadd.vv v11, v9, v10
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v11, v0
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 4)
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 2)
@@ -1006,11 +1003,8 @@ define <vscale x 2 x i32> @vmerge_smaller_vl_same_passthru(<vscale x 2 x i32> %p
define <vscale x 2 x i32> @vmerge_larger_vl_same_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: vmerge_larger_vl_same_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT: vmv1r.v v11, v8
-; CHECK-NEXT: vadd.vv v11, v9, v10
-; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v11, v0
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 2)
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 3)
@@ -1051,10 +1045,8 @@ define <vscale x 2 x i32> @vmerge_larger_vl_
diff erent_passthru(<vscale x 2 x i32
define <vscale x 2 x i32> @vmerge_smaller_vl_poison_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: vmerge_smaller_vl_poison_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 3, e32, m1, ta, ma
-; CHECK-NEXT: vadd.vv v9, v9, v10
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 3)
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 2)
@@ -1065,10 +1057,8 @@ define <vscale x 2 x i32> @vmerge_smaller_vl_poison_passthru(<vscale x 2 x i32>
define <vscale x 2 x i32> @vmerge_larger_vl_poison_passthru(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, <vscale x 2 x i1> %m) {
; CHECK-LABEL: vmerge_larger_vl_poison_passthru:
; CHECK: # %bb.0:
-; CHECK-NEXT: vsetivli zero, 2, e32, m1, ta, ma
-; CHECK-NEXT: vadd.vv v9, v9, v10
-; CHECK-NEXT: vsetivli zero, 3, e32, m1, tu, ma
-; CHECK-NEXT: vmerge.vvm v8, v8, v9, v0
+; CHECK-NEXT: vsetivli zero, 2, e32, m1, tu, mu
+; CHECK-NEXT: vadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret
%a = call <vscale x 2 x i32> @llvm.riscv.vadd.nxv2i32.nxv2i32(<vscale x 2 x i32> poison, <vscale x 2 x i32> %x, <vscale x 2 x i32> %y, i64 2)
%b = call <vscale x 2 x i32> @llvm.riscv.vmerge.nxv2i32.nxv2i32(<vscale x 2 x i32> %passthru, <vscale x 2 x i32> %passthru, <vscale x 2 x i32> %a, <vscale x 2 x i1> %m, i64 3)
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