[llvm] 6b693f5 - [AMDGPU][AsmParser][NFC] Translate parsed DS instructions to MCInsts automatically.
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Wed Jul 19 03:31:05 PDT 2023
Author: Ivan Kosarev
Date: 2023-07-19T11:30:56+01:00
New Revision: 6b693f5e34059023ab01254d0bde73808702e67a
URL: https://github.com/llvm/llvm-project/commit/6b693f5e34059023ab01254d0bde73808702e67a
DIFF: https://github.com/llvm/llvm-project/commit/6b693f5e34059023ab01254d0bde73808702e67a.diff
LOG: [AMDGPU][AsmParser][NFC] Translate parsed DS instructions to MCInsts automatically.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D155620
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/DSInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index c493b887257513..b9443559132fbc 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1312,8 +1312,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
unsigned RegWidth);
void cvtMubufImpl(MCInst &Inst, const OperandVector &Operands,
bool IsAtomic);
- void cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
- bool IsGdsHardcoded);
public:
enum AMDGPUMatchResultTy {
@@ -1567,9 +1565,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
bool tryParseFmt(const char *Pref, int64_t MaxVal, int64_t &Val);
bool matchDfmtNfmt(int64_t &Dfmt, int64_t &Nfmt, StringRef FormatStr, SMLoc Loc);
- void cvtDSOffset01(MCInst &Inst, const OperandVector &Operands);
- void cvtDS(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, false); }
- void cvtDSGds(MCInst &Inst, const OperandVector &Operands) { cvtDSImpl(Inst, Operands, true); }
void cvtExp(MCInst &Inst, const OperandVector &Operands);
bool parseCnt(int64_t &IntVal);
@@ -6280,76 +6275,9 @@ ParseStatus AMDGPUAsmParser::parseBLGP(OperandVector &Operands) {
}
//===----------------------------------------------------------------------===//
-// ds
+// Exp
//===----------------------------------------------------------------------===//
-void AMDGPUAsmParser::cvtDSOffset01(MCInst &Inst,
- const OperandVector &Operands) {
- OptionalImmIndexMap OptionalIdx;
-
- for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
- AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
-
- // Add the register arguments
- if (Op.isReg()) {
- Op.addRegOperands(Inst, 1);
- continue;
- }
-
- // Handle optional arguments
- OptionalIdx[Op.getImmTy()] = i;
- }
-
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset0);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyOffset1);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
-
- Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
-}
-
-void AMDGPUAsmParser::cvtDSImpl(MCInst &Inst, const OperandVector &Operands,
- bool IsGdsHardcoded) {
- OptionalImmIndexMap OptionalIdx;
- const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
- AMDGPUOperand::ImmTy OffsetType = AMDGPUOperand::ImmTyOffset;
-
- for (unsigned i = 1, e = Operands.size(); i != e; ++i) {
- AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[i]);
-
- auto TiedTo =
- Desc.getOperandConstraint(Inst.getNumOperands(), MCOI::TIED_TO);
-
- if (TiedTo != -1) {
- assert((unsigned)TiedTo < Inst.getNumOperands());
- Inst.addOperand(Inst.getOperand(TiedTo));
- }
-
- // Add the register arguments
- if (Op.isReg()) {
- Op.addRegOperands(Inst, 1);
- continue;
- }
-
- if (Op.isToken() && Op.getToken() == "gds") {
- IsGdsHardcoded = true;
- continue;
- }
-
- // Handle optional arguments
- OptionalIdx[Op.getImmTy()] = i;
-
- if (Op.getImmTy() == AMDGPUOperand::ImmTySwizzle)
- OffsetType = AMDGPUOperand::ImmTySwizzle;
- }
-
- addOptionalImmOperand(Inst, Operands, OptionalIdx, OffsetType);
-
- if (!IsGdsHardcoded) {
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyGDS);
- }
- Inst.addOperand(MCOperand::createReg(AMDGPU::M0)); // m0
-}
-
void AMDGPUAsmParser::cvtExp(MCInst &Inst, const OperandVector &Operands) {
OptionalImmIndexMap OptionalIdx;
diff --git a/llvm/lib/Target/AMDGPU/DSInstructions.td b/llvm/lib/Target/AMDGPU/DSInstructions.td
index ee7c8478c1fff1..85a3f763cd5a20 100644
--- a/llvm/lib/Target/AMDGPU/DSInstructions.td
+++ b/llvm/lib/Target/AMDGPU/DSInstructions.td
@@ -26,8 +26,6 @@ class DS_Pseudo <string opName, dag outs, dag ins, string asmOps, list<dag> patt
let isPseudo = 1;
let isCodeGenOnly = 1;
- let AsmMatchConverter = "cvtDS";
-
string Mnemonic = opName;
string AsmOperands = asmOps;
@@ -65,7 +63,6 @@ class DS_Real <DS_Pseudo ps, string opName = ps.Mnemonic> :
// copy relevant pseudo op flags
let SubtargetPredicate = ps.SubtargetPredicate;
let OtherPredicates = ps.OtherPredicates;
- let AsmMatchConverter = ps.AsmMatchConverter;
let SchedRW = ps.SchedRW;
let mayLoad = ps.mayLoad;
let mayStore = ps.mayStore;
@@ -164,7 +161,6 @@ class DS_1A2D_Off8_NORET <string opName, RegisterClass rc = VGPR_32,
let has_vdst = 0;
let has_offset = 0;
- let AsmMatchConverter = "cvtDSOffset01";
}
multiclass DS_1A2D_Off8_NORET_mc <string opName, RegisterClass rc = VGPR_32> {
@@ -187,7 +183,6 @@ class DS_0A1D_RET_GDS<string opName, RegisterClass rc = VGPR_32, RegisterClass s
let has_data1 = 0;
let has_gds = 0;
let gdsValue = 1;
- let AsmMatchConverter = "cvtDSGds";
let hasSideEffects = 1;
}
@@ -262,8 +257,6 @@ class DS_1A2D_Off8_RET<string opName,
" $vdst, $addr, $data0, $data1$offset0$offset1$gds"> {
let has_offset = 0;
- let AsmMatchConverter = "cvtDSOffset01";
-
let hasPostISelHook = 1;
}
@@ -325,7 +318,6 @@ class DS_1A_Off8_RET <string opName, RegisterClass rc = VGPR_32>
let has_offset = 0;
let has_data0 = 0;
let has_data1 = 0;
- let AsmMatchConverter = "cvtDSOffset01";
}
multiclass DS_1A_Off8_RET_mc <string opName, RegisterClass rc = VGPR_32> {
@@ -345,7 +337,6 @@ class DS_1A_RET_GDS <string opName> : DS_Pseudo<opName,
let has_data1 = 0;
let has_gds = 0;
let gdsValue = 1;
- let AsmMatchConverter = "cvtDSGds";
}
class DS_0A_RET <string opName> : DS_Pseudo<opName,
@@ -393,7 +384,6 @@ class DS_GWS <string opName, dag ins, string asmOps>
let has_gds = 0;
let gdsValue = 1;
- let AsmMatchConverter = "cvtDSGds";
}
class DS_GWS_0D <string opName>
@@ -417,7 +407,6 @@ class DS_VOID <string opName> : DS_Pseudo<opName,
let mayStore = 0;
let hasSideEffects = 1;
let UseNamedOperandTable = 0;
- let AsmMatchConverter = "";
let has_vdst = 0;
let has_addr = 0;
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