[PATCH] D155626: [DAG][AArch64] Fix truncated vscale constant types

[Dave Green via Phabricator via llvm-commits]

dmgreen updated this revision to Diff 541922.
dmgreen added a comment.

Thanks for checking!

This version adds a special case for i1 to the assert.


CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155626/new/

https://reviews.llvm.org/D155626

Files:
  llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
  llvm/test/CodeGen/AArch64/sve-vscale.ll


Index: llvm/test/CodeGen/AArch64/sve-vscale.ll
===================================================================
--- llvm/test/CodeGen/AArch64/sve-vscale.ll
+++ llvm/test/CodeGen/AArch64/sve-vscale.ll
@@ -101,6 +101,17 @@
   ret i32 %1
 }
 
+define i1 @rdvl_i1() {
+; CHECK-LABEL: rdvl_i1:
+; CHECK:         rdvl x8, #-1
+; CHECK-NEXT:    asr x8, x8, #4
+; CHECK-NEXT:    and w0, w8, #0x1
+; CHECK-NEXT:    ret
+  %a = tail call i64 @llvm.vscale.i64()
+  %b = trunc i64 %a to i1
+  ret i1 %b
+}
+
 ;
 ; CNTH
 ;
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -1942,7 +1942,7 @@
 
 SDValue SelectionDAG::getVScale(const SDLoc &DL, EVT VT, APInt MulImm,
                                 bool ConstantFold) {
-  assert(MulImm.getSignificantBits() <= VT.getSizeInBits() &&
+  assert((MulImm.getSignificantBits() <= VT.getSizeInBits() || VT == MVT::i1) &&
          "Immediate does not fit VT");
 
   MulImm = MulImm.sextOrTrunc(VT.getSizeInBits());


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