[PATCH] D155683: [RISCV] Fix the check assertion in hasMergeOp and hasMaskOp

[Jianjian Guan via Phabricator via llvm-commits]

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Because we have STRICT_FCVT_W_RV64 equal to ISD::FIRST_TARGET_STRICTFP_OPCODE, the check needs to be splitted into 2 parts.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155683

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp


Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -4683,7 +4683,10 @@
   assert(Opcode > RISCVISD::FIRST_NUMBER &&
          Opcode <= RISCVISD::STRICT_VFROUND_NOEXCEPT_VL &&
          "not a RISC-V target specific op");
-  assert(RISCVISD::STRICT_VFROUND_NOEXCEPT_VL - RISCVISD::FIRST_NUMBER == 421 &&
+  assert(RISCVISD::VFIRST_VL - RISCVISD::FIRST_NUMBER == 177 &&
+         RISCVISD::STRICT_VFROUND_NOEXCEPT_VL -
+                 ISD::FIRST_TARGET_STRICTFP_OPCODE ==
+             21 &&
          "adding target specific op should update this function");
   if (Opcode >= RISCVISD::ADD_VL && Opcode <= RISCVISD::FMAXNUM_VL)
     return true;
@@ -4701,7 +4704,10 @@
   assert(Opcode > RISCVISD::FIRST_NUMBER &&
          Opcode <= RISCVISD::STRICT_VFROUND_NOEXCEPT_VL &&
          "not a RISC-V target specific op");
-  assert(RISCVISD::STRICT_VFROUND_NOEXCEPT_VL - RISCVISD::FIRST_NUMBER == 421 &&
+  assert(RISCVISD::VFIRST_VL - RISCVISD::FIRST_NUMBER == 177 &&
+         RISCVISD::STRICT_VFROUND_NOEXCEPT_VL -
+                 ISD::FIRST_TARGET_STRICTFP_OPCODE ==
+             21 &&
          "adding target specific op should update this function");
   if (Opcode >= RISCVISD::TRUNCATE_VECTOR_VL && Opcode <= RISCVISD::SETCC_VL)
     return true;


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