[PATCH] D155646: [AMDGPU] Use AV regclass in wwm-reg spill pseudos for gfx908+

[Matt Arsenault via Phabricator via llvm-commits]

arsenm added inline comments.


================
Comment at: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp:1890
 
-  unsigned Opcode = getVectorRegSpillRestoreOpcode(VReg ? VReg : DestReg, RC,
-                                                   SpillSize, RI, *MFI);
+  bool HasVectorSuperClass = MF->getSubtarget<GCNSubtarget>().hasMAIInsts();
+  unsigned Opcode = getVectorRegSpillRestoreOpcode(
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You shouldn't need to consider the target, this should be solely determined from the class you already have


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155646/new/

https://reviews.llvm.org/D155646