[PATCH] D155502: [RISCV] Do not use FPR registers for fastcc if zfh/f/d is not specified in the architecture

[Yueh-Ting (eop) Chen via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rGeb89bf8d0d10: [RISCV] Do not use FPR registers for fastcc if zfh/f/d is not specified in the… (authored by eopXD).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155502/new/

https://reviews.llvm.org/D155502

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/fastcc-without-f-reg.ll

-------------- next part --------------
A non-text attachment was scrubbed...
Name: D155502.541612.patch
Type: text/x-patch
Size: 8072 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230718/416810dc/attachment.bin>