[PATCH] D155140: [RISCV] Add isMoveReg to vmv1r/vmv2r/vmv4r/vmv8r.v.

[Craig Topper via Phabricator via llvm-commits]

This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rGcdee88a2e061: [RISCV] Add isMoveReg to vmv1r/vmv2r/vmv4r/vmv8r.v. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155140/new/

https://reviews.llvm.org/D155140

Files:
  llvm/lib/Target/RISCV/RISCVInstrInfoV.td
  llvm/test/CodeGen/RISCV/rvv/copyprop.mir


Index: llvm/test/CodeGen/RISCV/rvv/copyprop.mir
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/copyprop.mir
+++ llvm/test/CodeGen/RISCV/rvv/copyprop.mir
@@ -23,8 +23,7 @@
   ; CHECK-NEXT:    li a2, 128
   ; CHECK-NEXT:    bgeu a0, a2, .LBB0_2
   ; CHECK-NEXT:  .LBB0_4: # %entry
-  ; CHECK-NEXT:    vmv1r.v v8, v9
-  ; CHECK-NEXT:    vse64.v v8, (a1)
+  ; CHECK-NEXT:    vse64.v v9, (a1)
   ; CHECK-NEXT:    ret
   entry:
     ret void
Index: llvm/lib/Target/RISCV/RISCVInstrInfoV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfoV.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfoV.td
@@ -1683,7 +1683,7 @@
 defm VCOMPRESS_V : VCPR_MV_Mask<"vcompress", 0b010111>;
 } // Constraints = "@earlyclobber $vd", RVVConstraint = Vcompress
 
-let hasSideEffects = 0, mayLoad = 0, mayStore = 0,
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isMoveReg = 1,
     RVVConstraint = NoConstraint in {
 // A future extension may relax the vector register alignment restrictions.
 foreach n = [1, 2, 4, 8] in {


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