[llvm] 46aec7b - [LoongArch][NFC] Revise instruction format to match lsx and lasx styles
via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 18 05:59:17 PDT 2023
Author: wanglei
Date: 2023-07-18T20:58:34+08:00
New Revision: 46aec7bc09472299c058bc8a64ef15e44c363933
URL: https://github.com/llvm/llvm-project/commit/46aec7bc09472299c058bc8a64ef15e44c363933
DIFF: https://github.com/llvm/llvm-project/commit/46aec7bc09472299c058bc8a64ef15e44c363933.diff
LOG: [LoongArch][NFC] Revise instruction format to match lsx and lasx styles
Replace lengthy `0b...` binary form with a unified 32-bit hexadecimal
representation for opcode. This reduces complexity when dealing with
opcode discontinuities.
Added:
Modified:
llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
index ba7a110175b135..eb49ae329ebe7e 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloat32InstrInfo.td
@@ -33,91 +33,91 @@ def loongarch_ftint : SDNode<"LoongArchISD::FTINT", SDT_LoongArchFTINT>;
let Predicates = [HasBasicF] in {
// Arithmetic Operation Instructions
-def FADD_S : FP_ALU_3R<0b00000001000000001, FPR32>;
-def FSUB_S : FP_ALU_3R<0b00000001000000101, FPR32>;
-def FMUL_S : FP_ALU_3R<0b00000001000001001, FPR32>;
-def FDIV_S : FP_ALU_3R<0b00000001000001101, FPR32>;
-def FMADD_S : FP_ALU_4R<0b000010000001, FPR32>;
-def FMSUB_S : FP_ALU_4R<0b000010000101, FPR32>;
-def FNMADD_S : FP_ALU_4R<0b000010001001, FPR32>;
-def FNMSUB_S : FP_ALU_4R<0b000010001101, FPR32>;
-def FMAX_S : FP_ALU_3R<0b00000001000010001, FPR32>;
-def FMIN_S : FP_ALU_3R<0b00000001000010101, FPR32>;
-def FMAXA_S : FP_ALU_3R<0b00000001000011001, FPR32>;
-def FMINA_S : FP_ALU_3R<0b00000001000011101, FPR32>;
-def FABS_S : FP_ALU_2R<0b0000000100010100000001, FPR32>;
-def FNEG_S : FP_ALU_2R<0b0000000100010100000101, FPR32>;
-def FSQRT_S : FP_ALU_2R<0b0000000100010100010001, FPR32>;
-def FRECIP_S : FP_ALU_2R<0b0000000100010100010101, FPR32>;
-def FRSQRT_S : FP_ALU_2R<0b0000000100010100011001, FPR32>;
-def FSCALEB_S : FP_ALU_3R<0b00000001000100001, FPR32>;
-def FLOGB_S : FP_ALU_2R<0b0000000100010100001001, FPR32>;
-def FCOPYSIGN_S : FP_ALU_3R<0b00000001000100101, FPR32>;
-def FCLASS_S : FP_ALU_2R<0b0000000100010100001101, FPR32>;
+def FADD_S : FP_ALU_3R<0x01008000>;
+def FSUB_S : FP_ALU_3R<0x01028000>;
+def FMUL_S : FP_ALU_3R<0x01048000>;
+def FDIV_S : FP_ALU_3R<0x01068000>;
+def FMADD_S : FP_ALU_4R<0x08100000>;
+def FMSUB_S : FP_ALU_4R<0x08500000>;
+def FNMADD_S : FP_ALU_4R<0x08900000>;
+def FNMSUB_S : FP_ALU_4R<0x08d00000>;
+def FMAX_S : FP_ALU_3R<0x01088000>;
+def FMIN_S : FP_ALU_3R<0x010a8000>;
+def FMAXA_S : FP_ALU_3R<0x010c8000>;
+def FMINA_S : FP_ALU_3R<0x010e8000>;
+def FABS_S : FP_ALU_2R<0x01140400>;
+def FNEG_S : FP_ALU_2R<0x01141400>;
+def FSQRT_S : FP_ALU_2R<0x01144400>;
+def FRECIP_S : FP_ALU_2R<0x01145400>;
+def FRSQRT_S : FP_ALU_2R<0x01146400>;
+def FSCALEB_S : FP_ALU_3R<0x01108000>;
+def FLOGB_S : FP_ALU_2R<0x01142400>;
+def FCOPYSIGN_S : FP_ALU_3R<0x01128000>;
+def FCLASS_S : FP_ALU_2R<0x01143400>;
// Comparison Instructions
-def FCMP_CAF_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CAF, FPR32>;
-def FCMP_CUN_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CUN, FPR32>;
-def FCMP_CEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CEQ, FPR32>;
-def FCMP_CUEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CUEQ, FPR32>;
-def FCMP_CLT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CLT, FPR32>;
-def FCMP_CULT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CULT, FPR32>;
-def FCMP_CLE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CLE, FPR32>;
-def FCMP_CULE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CULE, FPR32>;
-def FCMP_CNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CNE, FPR32>;
-def FCMP_COR_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_COR, FPR32>;
-def FCMP_CUNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_CUNE, FPR32>;
-def FCMP_SAF_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SAF, FPR32>;
-def FCMP_SUN_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SUN, FPR32>;
-def FCMP_SEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SEQ, FPR32>;
-def FCMP_SUEQ_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SUEQ, FPR32>;
-def FCMP_SLT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SLT, FPR32>;
-def FCMP_SULT_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SULT, FPR32>;
-def FCMP_SLE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SLE, FPR32>;
-def FCMP_SULE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SULE, FPR32>;
-def FCMP_SNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SNE, FPR32>;
-def FCMP_SOR_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SOR, FPR32>;
-def FCMP_SUNE_S : FP_CMP<FPCMP_OPC_S, FPCMP_COND_SUNE, FPR32>;
+def FCMP_CAF_S : FP_CMP<0x0c100000>;
+def FCMP_CUN_S : FP_CMP<0x0c140000>;
+def FCMP_CEQ_S : FP_CMP<0x0c120000>;
+def FCMP_CUEQ_S : FP_CMP<0x0c160000>;
+def FCMP_CLT_S : FP_CMP<0x0c110000>;
+def FCMP_CULT_S : FP_CMP<0x0c150000>;
+def FCMP_CLE_S : FP_CMP<0x0c130000>;
+def FCMP_CULE_S : FP_CMP<0x0c170000>;
+def FCMP_CNE_S : FP_CMP<0x0c180000>;
+def FCMP_COR_S : FP_CMP<0x0c1a0000>;
+def FCMP_CUNE_S : FP_CMP<0x0c1c0000>;
+def FCMP_SAF_S : FP_CMP<0x0c108000>;
+def FCMP_SUN_S : FP_CMP<0x0c148000>;
+def FCMP_SEQ_S : FP_CMP<0x0c128000>;
+def FCMP_SUEQ_S : FP_CMP<0x0c168000>;
+def FCMP_SLT_S : FP_CMP<0x0c118000>;
+def FCMP_SULT_S : FP_CMP<0x0c158000>;
+def FCMP_SLE_S : FP_CMP<0x0c138000>;
+def FCMP_SULE_S : FP_CMP<0x0c178000>;
+def FCMP_SNE_S : FP_CMP<0x0c188000>;
+def FCMP_SOR_S : FP_CMP<0x0c1a8000>;
+def FCMP_SUNE_S : FP_CMP<0x0c1c8000>;
// Conversion Instructions
-def FFINT_S_W : FP_CONV<0b0000000100011101000100, FPR32, FPR32>;
-def FTINT_W_S : FP_CONV<0b0000000100011011000001, FPR32, FPR32>;
-def FTINTRM_W_S : FP_CONV<0b0000000100011010000001, FPR32, FPR32>;
-def FTINTRP_W_S : FP_CONV<0b0000000100011010010001, FPR32, FPR32>;
-def FTINTRZ_W_S : FP_CONV<0b0000000100011010100001, FPR32, FPR32>;
-def FTINTRNE_W_S : FP_CONV<0b0000000100011010110001, FPR32, FPR32>;
-def FRINT_S : FP_CONV<0b0000000100011110010001, FPR32, FPR32>;
+def FFINT_S_W : FP_CONV<0x011d1000>;
+def FTINT_W_S : FP_CONV<0x011b0400>;
+def FTINTRM_W_S : FP_CONV<0x011a0400>;
+def FTINTRP_W_S : FP_CONV<0x011a4400>;
+def FTINTRZ_W_S : FP_CONV<0x011a8400>;
+def FTINTRNE_W_S : FP_CONV<0x011ac400>;
+def FRINT_S : FP_CONV<0x011e4400>;
// Move Instructions
-def FSEL_xS : FP_SEL<0b00001101000000, FPR32>;
-def FMOV_S : FP_MOV<0b0000000100010100100101, FPR32, FPR32>;
-def MOVGR2FR_W : FP_MOV<0b0000000100010100101001, FPR32, GPR>;
-def MOVFR2GR_S : FP_MOV<0b0000000100010100101101, GPR, FPR32>;
+def FSEL_xS : FP_SEL<0x0d000000>;
+def FMOV_S : FP_MOV<0x01149400>;
+def MOVGR2FR_W : FP_MOV<0x0114a400, FPR32, GPR>;
+def MOVFR2GR_S : FP_MOV<0x0114b400, GPR, FPR32>;
let hasSideEffects = 1 in {
-def MOVGR2FCSR : FP_MOV<0b0000000100010100110000, FCSR, GPR>;
-def MOVFCSR2GR : FP_MOV<0b0000000100010100110010, GPR, FCSR>;
+def MOVGR2FCSR : FP_MOV<0x0114c000, FCSR, GPR>;
+def MOVFCSR2GR : FP_MOV<0x0114c800, GPR, FCSR>;
} // hasSideEffects = 1
-def MOVFR2CF_xS : FP_MOV<0b0000000100010100110100, CFR, FPR32>;
-def MOVCF2FR_xS : FP_MOV<0b0000000100010100110101, FPR32, CFR>;
-def MOVGR2CF : FP_MOV<0b0000000100010100110110, CFR, GPR>;
-def MOVCF2GR : FP_MOV<0b0000000100010100110111, GPR, CFR>;
+def MOVFR2CF_xS : FP_MOV<0x0114d000, CFR, FPR32>;
+def MOVCF2FR_xS : FP_MOV<0x0114d400, FPR32, CFR>;
+def MOVGR2CF : FP_MOV<0x0114d800, CFR, GPR>;
+def MOVCF2GR : FP_MOV<0x0114dc00, GPR, CFR>;
// Branch Instructions
-def BCEQZ : FP_BRANCH<0b01001000>;
-def BCNEZ : FP_BRANCH<0b01001001>;
+def BCEQZ : FP_BRANCH<0x48000000>;
+def BCNEZ : FP_BRANCH<0x48000100>;
// Common Memory Access Instructions
-def FLD_S : FP_LOAD_2RI12<0b0010101100, FPR32>;
-def FST_S : FP_STORE_2RI12<0b0010101101, FPR32>;
-def FLDX_S : FP_LOAD_3R<0b00111000001100000, FPR32>;
-def FSTX_S : FP_STORE_3R<0b00111000001110000, FPR32>;
+def FLD_S : FP_LOAD_2RI12<0x2b000000>;
+def FST_S : FP_STORE_2RI12<0x2b400000>;
+def FLDX_S : FP_LOAD_3R<0x38300000>;
+def FSTX_S : FP_STORE_3R<0x38380000>;
// Bound Check Memory Access Instructions
-def FLDGT_S : FP_LOAD_3R<0b00111000011101000, FPR32>;
-def FLDLE_S : FP_LOAD_3R<0b00111000011101010, FPR32>;
-def FSTGT_S : FP_STORE_3R<0b00111000011101100, FPR32>;
-def FSTLE_S : FP_STORE_3R<0b00111000011101110, FPR32>;
+def FLDGT_S : FP_LOAD_3R<0x38740000>;
+def FLDLE_S : FP_LOAD_3R<0x38750000>;
+def FSTGT_S : FP_STORE_3R<0x38760000>;
+def FSTLE_S : FP_STORE_3R<0x38770000>;
// Pseudo instructions for spill/reload CFRs.
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
index f91ef7bc557668..5118474725b6c8 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloat64InstrInfo.td
@@ -17,111 +17,111 @@
let Predicates = [HasBasicD] in {
// Arithmetic Operation Instructions
-def FADD_D : FP_ALU_3R<0b00000001000000010, FPR64>;
-def FSUB_D : FP_ALU_3R<0b00000001000000110, FPR64>;
-def FMUL_D : FP_ALU_3R<0b00000001000001010, FPR64>;
-def FDIV_D : FP_ALU_3R<0b00000001000001110, FPR64>;
-def FMADD_D : FP_ALU_4R<0b000010000010, FPR64>;
-def FMSUB_D : FP_ALU_4R<0b000010000110, FPR64>;
-def FNMADD_D : FP_ALU_4R<0b000010001010, FPR64>;
-def FNMSUB_D : FP_ALU_4R<0b000010001110, FPR64>;
-def FMAX_D : FP_ALU_3R<0b00000001000010010, FPR64>;
-def FMIN_D : FP_ALU_3R<0b00000001000010110, FPR64>;
-def FMAXA_D : FP_ALU_3R<0b00000001000011010, FPR64>;
-def FMINA_D : FP_ALU_3R<0b00000001000011110, FPR64>;
-def FABS_D : FP_ALU_2R<0b0000000100010100000010, FPR64>;
-def FNEG_D : FP_ALU_2R<0b0000000100010100000110, FPR64>;
-def FSQRT_D : FP_ALU_2R<0b0000000100010100010010, FPR64>;
-def FRECIP_D : FP_ALU_2R<0b0000000100010100010110, FPR64>;
-def FRSQRT_D : FP_ALU_2R<0b0000000100010100011010, FPR64>;
-def FSCALEB_D : FP_ALU_3R<0b00000001000100010, FPR64>;
-def FLOGB_D : FP_ALU_2R<0b0000000100010100001010, FPR64>;
-def FCOPYSIGN_D : FP_ALU_3R<0b00000001000100110, FPR64>;
-def FCLASS_D : FP_ALU_2R<0b0000000100010100001110, FPR64>;
+def FADD_D : FP_ALU_3R<0x01010000, FPR64>;
+def FSUB_D : FP_ALU_3R<0x01030000, FPR64>;
+def FMUL_D : FP_ALU_3R<0x01050000, FPR64>;
+def FDIV_D : FP_ALU_3R<0x01070000, FPR64>;
+def FMADD_D : FP_ALU_4R<0x08200000, FPR64>;
+def FMSUB_D : FP_ALU_4R<0x08600000, FPR64>;
+def FNMADD_D : FP_ALU_4R<0x08a00000, FPR64>;
+def FNMSUB_D : FP_ALU_4R<0x08e00000, FPR64>;
+def FMAX_D : FP_ALU_3R<0x01090000, FPR64>;
+def FMIN_D : FP_ALU_3R<0x010b0000, FPR64>;
+def FMAXA_D : FP_ALU_3R<0x010d0000, FPR64>;
+def FMINA_D : FP_ALU_3R<0x010f0000, FPR64>;
+def FABS_D : FP_ALU_2R<0x01140800, FPR64>;
+def FNEG_D : FP_ALU_2R<0x01141800, FPR64>;
+def FSQRT_D : FP_ALU_2R<0x01144800, FPR64>;
+def FRECIP_D : FP_ALU_2R<0x01145800, FPR64>;
+def FRSQRT_D : FP_ALU_2R<0x01146800, FPR64>;
+def FSCALEB_D : FP_ALU_3R<0x01110000, FPR64>;
+def FLOGB_D : FP_ALU_2R<0x01142800, FPR64>;
+def FCOPYSIGN_D : FP_ALU_3R<0x01130000, FPR64>;
+def FCLASS_D : FP_ALU_2R<0x01143800, FPR64>;
// Comparison Instructions
-def FCMP_CAF_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CAF, FPR64>;
-def FCMP_CUN_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CUN, FPR64>;
-def FCMP_CEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CEQ, FPR64>;
-def FCMP_CUEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CUEQ, FPR64>;
-def FCMP_CLT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CLT, FPR64>;
-def FCMP_CULT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CULT, FPR64>;
-def FCMP_CLE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CLE, FPR64>;
-def FCMP_CULE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CULE, FPR64>;
-def FCMP_CNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CNE, FPR64>;
-def FCMP_COR_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_COR, FPR64>;
-def FCMP_CUNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_CUNE, FPR64>;
-def FCMP_SAF_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SAF, FPR64>;
-def FCMP_SUN_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SUN, FPR64>;
-def FCMP_SEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SEQ, FPR64>;
-def FCMP_SUEQ_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SUEQ, FPR64>;
-def FCMP_SLT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SLT, FPR64>;
-def FCMP_SULT_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SULT, FPR64>;
-def FCMP_SLE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SLE, FPR64>;
-def FCMP_SULE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SULE, FPR64>;
-def FCMP_SNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SNE, FPR64>;
-def FCMP_SOR_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SOR, FPR64>;
-def FCMP_SUNE_D : FP_CMP<FPCMP_OPC_D, FPCMP_COND_SUNE, FPR64>;
+def FCMP_CAF_D : FP_CMP<0x0c200000, FPR64>;
+def FCMP_CUN_D : FP_CMP<0x0c240000, FPR64>;
+def FCMP_CEQ_D : FP_CMP<0x0c220000, FPR64>;
+def FCMP_CUEQ_D : FP_CMP<0x0c260000, FPR64>;
+def FCMP_CLT_D : FP_CMP<0x0c210000, FPR64>;
+def FCMP_CULT_D : FP_CMP<0x0c250000, FPR64>;
+def FCMP_CLE_D : FP_CMP<0x0c230000, FPR64>;
+def FCMP_CULE_D : FP_CMP<0x0c270000, FPR64>;
+def FCMP_CNE_D : FP_CMP<0x0c280000, FPR64>;
+def FCMP_COR_D : FP_CMP<0x0c2a0000, FPR64>;
+def FCMP_CUNE_D : FP_CMP<0x0c2c0000, FPR64>;
+def FCMP_SAF_D : FP_CMP<0x0c208000, FPR64>;
+def FCMP_SUN_D : FP_CMP<0x0c248000, FPR64>;
+def FCMP_SEQ_D : FP_CMP<0x0c228000, FPR64>;
+def FCMP_SUEQ_D : FP_CMP<0x0c268000, FPR64>;
+def FCMP_SLT_D : FP_CMP<0x0c218000, FPR64>;
+def FCMP_SULT_D : FP_CMP<0x0c258000, FPR64>;
+def FCMP_SLE_D : FP_CMP<0x0c238000, FPR64>;
+def FCMP_SULE_D : FP_CMP<0x0c278000, FPR64>;
+def FCMP_SNE_D : FP_CMP<0x0c288000, FPR64>;
+def FCMP_SOR_D : FP_CMP<0x0c2a8000, FPR64>;
+def FCMP_SUNE_D : FP_CMP<0x0c2c8000, FPR64>;
// Conversion Instructions
-def FFINT_S_L : FP_CONV<0b0000000100011101000110, FPR32, FPR64>;
-def FTINT_L_S : FP_CONV<0b0000000100011011001001, FPR64, FPR32>;
-def FTINTRM_L_S : FP_CONV<0b0000000100011010001001, FPR64, FPR32>;
-def FTINTRP_L_S : FP_CONV<0b0000000100011010011001, FPR64, FPR32>;
-def FTINTRZ_L_S : FP_CONV<0b0000000100011010101001, FPR64, FPR32>;
-def FTINTRNE_L_S : FP_CONV<0b0000000100011010111001, FPR64, FPR32>;
-def FCVT_S_D : FP_CONV<0b0000000100011001000110, FPR32, FPR64>;
-def FCVT_D_S : FP_CONV<0b0000000100011001001001, FPR64, FPR32>;
-def FFINT_D_W : FP_CONV<0b0000000100011101001000, FPR64, FPR32>;
-def FFINT_D_L : FP_CONV<0b0000000100011101001010, FPR64, FPR64>;
-def FTINT_W_D : FP_CONV<0b0000000100011011000010, FPR32, FPR64>;
-def FTINT_L_D : FP_CONV<0b0000000100011011001010, FPR64, FPR64>;
-def FTINTRM_W_D : FP_CONV<0b0000000100011010000010, FPR32, FPR64>;
-def FTINTRM_L_D : FP_CONV<0b0000000100011010001010, FPR64, FPR64>;
-def FTINTRP_W_D : FP_CONV<0b0000000100011010010010, FPR32, FPR64>;
-def FTINTRP_L_D : FP_CONV<0b0000000100011010011010, FPR64, FPR64>;
-def FTINTRZ_W_D : FP_CONV<0b0000000100011010100010, FPR32, FPR64>;
-def FTINTRZ_L_D : FP_CONV<0b0000000100011010101010, FPR64, FPR64>;
-def FTINTRNE_W_D : FP_CONV<0b0000000100011010110010, FPR32, FPR64>;
-def FTINTRNE_L_D : FP_CONV<0b0000000100011010111010, FPR64, FPR64>;
-def FRINT_D : FP_CONV<0b0000000100011110010010, FPR64, FPR64>;
+def FFINT_S_L : FP_CONV<0x011d1800, FPR32, FPR64>;
+def FTINT_L_S : FP_CONV<0x011b2400, FPR64, FPR32>;
+def FTINTRM_L_S : FP_CONV<0x011a2400, FPR64, FPR32>;
+def FTINTRP_L_S : FP_CONV<0x011a6400, FPR64, FPR32>;
+def FTINTRZ_L_S : FP_CONV<0x011aa400, FPR64, FPR32>;
+def FTINTRNE_L_S : FP_CONV<0x011ae400, FPR64, FPR32>;
+def FCVT_S_D : FP_CONV<0x01191800, FPR32, FPR64>;
+def FCVT_D_S : FP_CONV<0x01192400, FPR64, FPR32>;
+def FFINT_D_W : FP_CONV<0x011d2000, FPR64, FPR32>;
+def FFINT_D_L : FP_CONV<0x011d2800, FPR64, FPR64>;
+def FTINT_W_D : FP_CONV<0x011b0800, FPR32, FPR64>;
+def FTINT_L_D : FP_CONV<0x011b2800, FPR64, FPR64>;
+def FTINTRM_W_D : FP_CONV<0x011a0800, FPR32, FPR64>;
+def FTINTRM_L_D : FP_CONV<0x011a2800, FPR64, FPR64>;
+def FTINTRP_W_D : FP_CONV<0x011a4800, FPR32, FPR64>;
+def FTINTRP_L_D : FP_CONV<0x011a6800, FPR64, FPR64>;
+def FTINTRZ_W_D : FP_CONV<0x011a8800, FPR32, FPR64>;
+def FTINTRZ_L_D : FP_CONV<0x011aa800, FPR64, FPR64>;
+def FTINTRNE_W_D : FP_CONV<0x011ac800, FPR32, FPR64>;
+def FTINTRNE_L_D : FP_CONV<0x011ae800, FPR64, FPR64>;
+def FRINT_D : FP_CONV<0x011e4800, FPR64, FPR64>;
// Move Instructions
-def FMOV_D : FP_MOV<0b0000000100010100100110, FPR64, FPR64>;
-def MOVFRH2GR_S : FP_MOV<0b0000000100010100101111, GPR, FPR64>;
+def FMOV_D : FP_MOV<0x01149800, FPR64, FPR64>;
+def MOVFRH2GR_S : FP_MOV<0x0114bc00, GPR, FPR64>;
let isCodeGenOnly = 1 in {
-def MOVFR2GR_S_64 : FP_MOV<0b0000000100010100101101, GPR, FPR64>;
-def FSEL_xD : FP_SEL<0b00001101000000, FPR64>;
+def MOVFR2GR_S_64 : FP_MOV<0x0114b400, GPR, FPR64>;
+def FSEL_xD : FP_SEL<0x0d000000, FPR64>;
} // isCodeGenOnly = 1
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out" in {
-def MOVGR2FRH_W : FPFmtMOV<0b0000000100010100101011, (outs FPR64:$out),
+def MOVGR2FRH_W : FPFmtMOV<0x0114ac00, (outs FPR64:$out),
(ins FPR64:$dst, GPR:$src),
"$dst, $src">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0, Constraints = "$dst = $out"
// Common Memory Access Instructions
-def FLD_D : FP_LOAD_2RI12<0b0010101110, FPR64>;
-def FST_D : FP_STORE_2RI12<0b0010101111, FPR64>;
-def FLDX_D : FP_LOAD_3R<0b00111000001101000, FPR64>;
-def FSTX_D : FP_STORE_3R<0b00111000001111000, FPR64>;
+def FLD_D : FP_LOAD_2RI12<0x2b800000, FPR64>;
+def FST_D : FP_STORE_2RI12<0x2bc00000, FPR64>;
+def FLDX_D : FP_LOAD_3R<0x38340000, FPR64>;
+def FSTX_D : FP_STORE_3R<0x383c0000, FPR64>;
// Bound Check Memory Access Instructions
-def FLDGT_D : FP_LOAD_3R<0b00111000011101001, FPR64>;
-def FLDLE_D : FP_LOAD_3R<0b00111000011101011, FPR64>;
-def FSTGT_D : FP_STORE_3R<0b00111000011101101, FPR64>;
-def FSTLE_D : FP_STORE_3R<0b00111000011101111, FPR64>;
+def FLDGT_D : FP_LOAD_3R<0x38748000, FPR64>;
+def FLDLE_D : FP_LOAD_3R<0x38758000, FPR64>;
+def FSTGT_D : FP_STORE_3R<0x38768000, FPR64>;
+def FSTLE_D : FP_STORE_3R<0x38778000, FPR64>;
} // Predicates = [HasBasicD]
// Instructions only available on LA64
let Predicates = [HasBasicD, IsLA64] in {
-def MOVGR2FR_D : FP_MOV<0b0000000100010100101010, FPR64, GPR>;
-def MOVFR2GR_D : FP_MOV<0b0000000100010100101110, GPR, FPR64>;
+def MOVGR2FR_D : FP_MOV<0x0114a800, FPR64, GPR>;
+def MOVFR2GR_D : FP_MOV<0x0114b800, GPR, FPR64>;
} // Predicates = [HasBasicD, IsLA64]
// Instructions only available on LA32
let Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1 in {
-def MOVGR2FR_W_64 : FP_MOV<0b0000000100010100101001, FPR64, GPR>;
+def MOVGR2FR_W_64 : FP_MOV<0x0114a400, FPR64, GPR>;
} // Predicates = [HasBasicD, IsLA32], isCodeGenOnly = 1
//===----------------------------------------------------------------------===//
diff --git a/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
index f9589699fd246b..f853fca5c8b675 100644
--- a/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
+++ b/llvm/lib/Target/LoongArch/LoongArchFloatInstrFormats.td
@@ -31,27 +31,27 @@ class deriveFPInsnMnemonic<string name> {
// 2R-type
// <opcode | fj | fd>
-class FPFmt2R<bits<22> op, dag outs, dag ins, string opnstr,
+class FPFmt2R<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveFPInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> fj;
bits<5> fd;
- let Inst{31-10} = op;
+ let Inst{31-0} = op;
let Inst{9-5} = fj;
let Inst{4-0} = fd;
}
// 3R-type
// <opcode | fk | fj | fd>
-class FPFmt3R<bits<17> op, dag outs, dag ins, string opnstr,
+class FPFmt3R<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveFPInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> fk;
bits<5> fj;
bits<5> fd;
- let Inst{31-15} = op;
+ let Inst{31-0} = op;
let Inst{14-10} = fk;
let Inst{9-5} = fj;
let Inst{4-0} = fd;
@@ -59,7 +59,7 @@ class FPFmt3R<bits<17> op, dag outs, dag ins, string opnstr,
// 4R-type
// <opcode | fa | fk | fj | fd>
-class FPFmt4R<bits<12> op, dag outs, dag ins, string opnstr,
+class FPFmt4R<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveFPInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> fa;
@@ -67,7 +67,7 @@ class FPFmt4R<bits<12> op, dag outs, dag ins, string opnstr,
bits<5> fj;
bits<5> fd;
- let Inst{31-20} = op;
+ let Inst{31-0} = op;
let Inst{19-15} = fa;
let Inst{14-10} = fk;
let Inst{9-5} = fj;
@@ -76,54 +76,51 @@ class FPFmt4R<bits<12> op, dag outs, dag ins, string opnstr,
// 2RI12-type
// <opcode | I12 | rj | fd>
-class FPFmt2RI12<bits<10> op, dag outs, dag ins, string opnstr,
+class FPFmt2RI12<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveFPInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<12> imm12;
bits<5> rj;
bits<5> fd;
- let Inst{31-22} = op;
+ let Inst{31-0} = op;
let Inst{21-10} = imm12;
let Inst{9-5} = rj;
let Inst{4-0} = fd;
}
// FmtFCMP
-// <opcode | cond | fk | fj | 0b00 | cd>
-class FPFmtFCMP<bits<12> op, bits<5> cond, dag outs, dag ins, string opnstr,
+// <opcode | fk | fj | cd>
+class FPFmtFCMP<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveFPInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> fk;
bits<5> fj;
bits<3> cd;
- let Inst{31-20} = op;
- let Inst{19-15} = cond;
+ let Inst{31-0} = op;
let Inst{14-10} = fk;
let Inst{9-5} = fj;
- let Inst{4-3} = 0b00;
let Inst{2-0} = cd;
}
// FPFmtBR
-// <opcode[7:2] | I21[15:0] | opcode[1:0] | cj | I21[20:16]>
-class FPFmtBR<bits<8> opcode, dag outs, dag ins, string opnstr,
+// <opcode | I21[15:0] | cj | I21[20:16]>
+class FPFmtBR<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveFPInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<21> imm21;
bits<3> cj;
- let Inst{31-26} = opcode{7-2};
+ let Inst{31-0} = op;
let Inst{25-10} = imm21{15-0};
- let Inst{9-8} = opcode{1-0};
let Inst{7-5} = cj;
let Inst{4-0} = imm21{20-16};
}
// FmtFSEL
// <opcode | ca | fk | fj | fd>
-class FPFmtFSEL<bits<14> op, dag outs, dag ins, string opnstr,
+class FPFmtFSEL<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveFPInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<3> ca;
@@ -131,7 +128,7 @@ class FPFmtFSEL<bits<14> op, dag outs, dag ins, string opnstr,
bits<5> fj;
bits<5> fd;
- let Inst{31-18} = op;
+ let Inst{31-0} = op;
let Inst{17-15} = ca;
let Inst{14-10} = fk;
let Inst{9-5} = fj;
@@ -140,27 +137,27 @@ class FPFmtFSEL<bits<14> op, dag outs, dag ins, string opnstr,
// FPFmtMOV
// <opcode | src | dst>
-class FPFmtMOV<bits<22> op, dag outs, dag ins, string opnstr,
+class FPFmtMOV<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveFPInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> src;
bits<5> dst;
- let Inst{31-10} = op;
+ let Inst{31-0} = op;
let Inst{9-5} = src;
let Inst{4-0} = dst;
}
// FPFmtMEM
// <opcode | rk | rj | fd>
-class FPFmtMEM<bits<17> op, dag outs, dag ins, string opnstr,
+class FPFmtMEM<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveFPInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> rk;
bits<5> rj;
bits<5> fd;
- let Inst{31-15} = op;
+ let Inst{31-0} = op;
let Inst{14-10} = rk;
let Inst{9-5} = rj;
let Inst{4-0} = fd;
@@ -171,41 +168,32 @@ class FPFmtMEM<bits<17> op, dag outs, dag ins, string opnstr,
//===----------------------------------------------------------------------===//
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-class FP_ALU_2R<bits<22> op, RegisterClass rc>
+class FP_ALU_2R<bits<32> op, RegisterClass rc = FPR32>
: FPFmt2R<op, (outs rc:$fd), (ins rc:$fj), "$fd, $fj">;
-class FP_ALU_3R<bits<17> op, RegisterClass rc>
+class FP_ALU_3R<bits<32> op, RegisterClass rc = FPR32>
: FPFmt3R<op, (outs rc:$fd), (ins rc:$fj, rc:$fk), "$fd, $fj, $fk">;
-class FP_ALU_4R<bits<12> op, RegisterClass rc>
+class FP_ALU_4R<bits<32> op, RegisterClass rc = FPR32>
: FPFmt4R<op, (outs rc:$fd), (ins rc:$fj, rc:$fk, rc:$fa),
"$fd, $fj, $fk, $fa">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
-class FPCMPOpc<bits<12> value> {
- bits<12> val = value;
-}
-
-class FPCMPCond<bits<5> value> {
- bits<5> val = value;
-}
-
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-class FP_CMP<FPCMPOpc op, FPCMPCond cond, RegisterClass rc>
- : FPFmtFCMP<op.val, cond.val, (outs CFR:$cd), (ins rc:$fj, rc:$fk),
- "$cd, $fj, $fk">;
+class FP_CMP<bits<32> op, RegisterClass rc = FPR32>
+ : FPFmtFCMP<op, (outs CFR:$cd), (ins rc:$fj, rc:$fk), "$cd, $fj, $fk">;
-class FP_CONV<bits<22> op, RegisterClass rcd, RegisterClass rcs>
+class FP_CONV<bits<32> op, RegisterClass rcd = FPR32, RegisterClass rcs = FPR32>
: FPFmt2R<op, (outs rcd:$fd), (ins rcs:$fj), "$fd, $fj">;
-class FP_MOV<bits<22> op, RegisterClass rcd, RegisterClass rcs>
+class FP_MOV<bits<32> op, RegisterClass rcd = FPR32, RegisterClass rcs = FPR32>
: FPFmtMOV<op, (outs rcd:$dst), (ins rcs:$src), "$dst, $src">;
-class FP_SEL<bits<14> op, RegisterClass rc>
+class FP_SEL<bits<32> op, RegisterClass rc = FPR32>
: FPFmtFSEL<op, (outs rc:$fd), (ins rc:$fj, rc:$fk, CFR:$ca),
"$fd, $fj, $fk, $ca">;
-class FP_BRANCH<bits<8> opcode>
+class FP_BRANCH<bits<32> opcode>
: FPFmtBR<opcode, (outs), (ins CFR:$cj, simm21_lsl2:$imm21),
"$cj, $imm21"> {
let isBranch = 1;
@@ -214,45 +202,19 @@ class FP_BRANCH<bits<8> opcode>
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
-class FP_LOAD_3R<bits<17> op, RegisterClass rc>
+class FP_LOAD_3R<bits<32> op, RegisterClass rc = FPR32>
: FPFmtMEM<op, (outs rc:$fd), (ins GPR:$rj, GPR:$rk),
"$fd, $rj, $rk">;
-class FP_LOAD_2RI12<bits<10> op, RegisterClass rc>
+class FP_LOAD_2RI12<bits<32> op, RegisterClass rc = FPR32>
: FPFmt2RI12<op, (outs rc:$fd), (ins GPR:$rj, simm12:$imm12),
"$fd, $rj, $imm12">;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
-class FP_STORE_3R<bits<17> op, RegisterClass rc>
+class FP_STORE_3R<bits<32> op, RegisterClass rc = FPR32>
: FPFmtMEM<op, (outs), (ins rc:$fd, GPR:$rj, GPR:$rk),
"$fd, $rj, $rk">;
-class FP_STORE_2RI12<bits<10> op, RegisterClass rc>
+class FP_STORE_2RI12<bits<32> op, RegisterClass rc = FPR32>
: FPFmt2RI12<op, (outs), (ins rc:$fd, GPR:$rj, simm12:$imm12),
"$fd, $rj, $imm12">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
-
-def FPCMP_OPC_S : FPCMPOpc<0b000011000001>;
-def FPCMP_OPC_D : FPCMPOpc<0b000011000010>;
-
-def FPCMP_COND_CAF : FPCMPCond<0x0>;
-def FPCMP_COND_CUN : FPCMPCond<0x8>;
-def FPCMP_COND_CEQ : FPCMPCond<0x4>;
-def FPCMP_COND_CUEQ : FPCMPCond<0xC>;
-def FPCMP_COND_CLT : FPCMPCond<0x2>;
-def FPCMP_COND_CULT : FPCMPCond<0xA>;
-def FPCMP_COND_CLE : FPCMPCond<0x6>;
-def FPCMP_COND_CULE : FPCMPCond<0xE>;
-def FPCMP_COND_CNE : FPCMPCond<0x10>;
-def FPCMP_COND_COR : FPCMPCond<0x14>;
-def FPCMP_COND_CUNE : FPCMPCond<0x18>;
-def FPCMP_COND_SAF : FPCMPCond<0x1>;
-def FPCMP_COND_SUN : FPCMPCond<0x9>;
-def FPCMP_COND_SEQ : FPCMPCond<0x5>;
-def FPCMP_COND_SUEQ : FPCMPCond<0xD>;
-def FPCMP_COND_SLT : FPCMPCond<0x3>;
-def FPCMP_COND_SULT : FPCMPCond<0xB>;
-def FPCMP_COND_SLE : FPCMPCond<0x7>;
-def FPCMP_COND_SULE : FPCMPCond<0xF>;
-def FPCMP_COND_SNE : FPCMPCond<0x11>;
-def FPCMP_COND_SOR : FPCMPCond<0x15>;
-def FPCMP_COND_SUNE : FPCMPCond<0x19>;
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
index 9288cabd17ec41..6ffc8823baee01 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrFormats.td
@@ -48,27 +48,27 @@ class deriveInsnMnemonic<string name> {
// 2R-type
// <opcode | rj | rd>
-class Fmt2R<bits<22> op, dag outs, dag ins, string opnstr,
+class Fmt2R<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> rj;
bits<5> rd;
- let Inst{31-10} = op;
+ let Inst{31-0} = op;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
}
// 3R-type
// <opcode | rk | rj | rd>
-class Fmt3R<bits<17> op, dag outs, dag ins, string opnstr,
+class Fmt3R<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> rk;
bits<5> rj;
bits<5> rd;
- let Inst{31-15} = op;
+ let Inst{31-0} = op;
let Inst{14-10} = rk;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
@@ -76,7 +76,7 @@ class Fmt3R<bits<17> op, dag outs, dag ins, string opnstr,
// 3RI2-type
// <opcode | I2 | rk | rj | rd>
-class Fmt3RI2<bits<15> op, dag outs, dag ins, string opnstr,
+class Fmt3RI2<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<2> imm2;
@@ -84,7 +84,7 @@ class Fmt3RI2<bits<15> op, dag outs, dag ins, string opnstr,
bits<5> rj;
bits<5> rd;
- let Inst{31-17} = op;
+ let Inst{31-0} = op;
let Inst{16-15} = imm2;
let Inst{14-10} = rk;
let Inst{9-5} = rj;
@@ -93,7 +93,7 @@ class Fmt3RI2<bits<15> op, dag outs, dag ins, string opnstr,
// 3RI3-type
// <opcode | I3 | rk | rj | rd>
-class Fmt3RI3<bits<14> op, dag outs, dag ins, string opnstr,
+class Fmt3RI3<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<3> imm3;
@@ -101,7 +101,7 @@ class Fmt3RI3<bits<14> op, dag outs, dag ins, string opnstr,
bits<5> rj;
bits<5> rd;
- let Inst{31-18} = op;
+ let Inst{31-0} = op;
let Inst{17-15} = imm3;
let Inst{14-10} = rk;
let Inst{9-5} = rj;
@@ -110,14 +110,14 @@ class Fmt3RI3<bits<14> op, dag outs, dag ins, string opnstr,
// 2RI5-type
// <opcode | I5 | rj | rd>
-class Fmt2RI5<bits<17> op, dag outs, dag ins, string opnstr,
+class Fmt2RI5<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> imm5;
bits<5> rj;
bits<5> rd;
- let Inst{31-15} = op;
+ let Inst{31-0} = op;
let Inst{14-10} = imm5;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
@@ -125,14 +125,14 @@ class Fmt2RI5<bits<17> op, dag outs, dag ins, string opnstr,
// 2RI6-type
// <opcode | I6 | rj | rd>
-class Fmt2RI6<bits<16> op, dag outs, dag ins, string opnstr,
+class Fmt2RI6<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<6> imm6;
bits<5> rj;
bits<5> rd;
- let Inst{31-16} = op;
+ let Inst{31-0} = op;
let Inst{15-10} = imm6;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
@@ -140,14 +140,14 @@ class Fmt2RI6<bits<16> op, dag outs, dag ins, string opnstr,
// 2RI8-type
// <opcode | I8 | rj | rd>
-class Fmt2RI8<bits<14> op, dag outs, dag ins, string opnstr,
+class Fmt2RI8<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<8> imm8;
bits<5> rj;
bits<5> rd;
- let Inst{31-18} = op;
+ let Inst{31-0} = op;
let Inst{17-10} = imm8;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
@@ -155,14 +155,14 @@ class Fmt2RI8<bits<14> op, dag outs, dag ins, string opnstr,
// 2RI12-type
// <opcode | I12 | rj | rd>
-class Fmt2RI12<bits<10> op, dag outs, dag ins, string opnstr,
+class Fmt2RI12<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<12> imm12;
bits<5> rj;
bits<5> rd;
- let Inst{31-22} = op;
+ let Inst{31-0} = op;
let Inst{21-10} = imm12;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
@@ -170,14 +170,14 @@ class Fmt2RI12<bits<10> op, dag outs, dag ins, string opnstr,
// 2RI14-type
// <opcode | I14 | rj | rd>
-class Fmt2RI14<bits<8> op, dag outs, dag ins, string opnstr,
+class Fmt2RI14<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<14> imm14;
bits<5> rj;
bits<5> rd;
- let Inst{31-24} = op;
+ let Inst{31-0} = op;
let Inst{23-10} = imm14;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
@@ -185,14 +185,14 @@ class Fmt2RI14<bits<8> op, dag outs, dag ins, string opnstr,
// 2RI16-type
// <opcode | I16 | rj | rd>
-class Fmt2RI16<bits<6> op, dag outs, dag ins, string opnstr,
+class Fmt2RI16<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<16> imm16;
bits<5> rj;
bits<5> rd;
- let Inst{31-26} = op;
+ let Inst{31-0} = op;
let Inst{25-10} = imm16;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
@@ -200,26 +200,26 @@ class Fmt2RI16<bits<6> op, dag outs, dag ins, string opnstr,
// 1RI20-type
// <opcode | I20 | rd>
-class Fmt1RI20<bits<7> op, dag outs, dag ins, string opnstr,
+class Fmt1RI20<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<20> imm20;
bits<5> rd;
- let Inst{31-25} = op;
+ let Inst{31-0} = op;
let Inst{24-5} = imm20;
let Inst{4-0} = rd;
}
// 1RI21-type
// <opcode | I21[15:0] | rj | I21[20:16]>
-class Fmt1RI21<bits<6> op, dag outs, dag ins, string opnstr,
+class Fmt1RI21<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<21> imm21;
bits<5> rj;
- let Inst{31-26} = op;
+ let Inst{31-0} = op;
let Inst{25-10} = imm21{15-0};
let Inst{9-5} = rj;
let Inst{4-0} = imm21{20-16};
@@ -227,30 +227,30 @@ class Fmt1RI21<bits<6> op, dag outs, dag ins, string opnstr,
// I15-type
// <opcode | I15>
-class FmtI15<bits<17> op, dag outs, dag ins, string opnstr,
+class FmtI15<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<15> imm15;
- let Inst{31-15} = op;
+ let Inst{31-0} = op;
let Inst{14-0} = imm15;
}
// I26-type
// <opcode | I26[15:0] | I26[25:16]>
-class FmtI26<bits<6> op, dag outs, dag ins, string opnstr,
+class FmtI26<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<26> imm26;
- let Inst{31-26} = op;
+ let Inst{31-0} = op;
let Inst{25-10} = imm26{15-0};
let Inst{9-0} = imm26{25-16};
}
// FmtBSTR_W
-// <opcode[11:1] | msbw | opcode[0] | lsbw | rj | rd>
-class FmtBSTR_W<bits<12> op, dag outs, dag ins, string opnstr,
+// <opcode | msbw | lsbw | rj | rd>
+class FmtBSTR_W<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> msbw;
@@ -258,9 +258,8 @@ class FmtBSTR_W<bits<12> op, dag outs, dag ins, string opnstr,
bits<5> rj;
bits<5> rd;
- let Inst{31-21} = op{11-1};
+ let Inst{31-0} = op;
let Inst{20-16} = msbw;
- let Inst{15} = op{0};
let Inst{14-10} = lsbw;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
@@ -268,7 +267,7 @@ class FmtBSTR_W<bits<12> op, dag outs, dag ins, string opnstr,
// FmtBSTR_D
// <opcode | msbd | lsbd | rj | rd>
-class FmtBSTR_D<bits<10> op, dag outs, dag ins, string opnstr,
+class FmtBSTR_D<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<6> msbd;
@@ -276,7 +275,7 @@ class FmtBSTR_D<bits<10> op, dag outs, dag ins, string opnstr,
bits<5> rj;
bits<5> rd;
- let Inst{31-22} = op;
+ let Inst{31-0} = op;
let Inst{21-16} = msbd;
let Inst{15-10} = lsbd;
let Inst{9-5} = rj;
@@ -284,17 +283,16 @@ class FmtBSTR_D<bits<10> op, dag outs, dag ins, string opnstr,
}
// FmtASRT
-// <opcode | rk | rj | 0x0>
-class FmtASRT<bits<17> op, dag outs, dag ins, string opnstr,
+// <opcode | rk | rj>
+class FmtASRT<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<5> rk;
bits<5> rj;
- let Inst{31-15} = op;
+ let Inst{31-0} = op;
let Inst{14-10} = rk;
let Inst{9-5} = rj;
- let Inst{4-0} = 0x0;
}
// FmtPRELD
@@ -326,29 +324,28 @@ class FmtPRELDX<dag outs, dag ins, string opnstr, list<dag> pattern = []>
}
// FmtCSR
-// <opcode[12:5] | csr_num | opcode[4:0] | rd>
-class FmtCSR<bits<13> op, dag outs, dag ins, string opnstr,
+// <opcode | csr_num | rd>
+class FmtCSR<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<14> csr_num;
bits<5> rd;
- let Inst{31-24} = op{12-5};
+ let Inst{31-0} = op;
let Inst{23-10} = csr_num;
- let Inst{9-5} = op{4-0};
let Inst{4-0} = rd;
}
// FmtCSRXCHG
// <opcode | csr_num | rj | rd>
-class FmtCSRXCHG<bits<8> op, dag outs, dag ins, string opnstr,
+class FmtCSRXCHG<bits<32> op, dag outs, dag ins, string opnstr,
list<dag> pattern = []>
: LAInst<outs, ins, deriveInsnMnemonic<NAME>.ret, opnstr, pattern> {
bits<14> csr_num;
bits<5> rj;
bits<5> rd;
- let Inst{31-24} = op;
+ let Inst{31-0} = op;
let Inst{23-10} = csr_num;
let Inst{9-5} = rj;
let Inst{4-0} = rd;
diff --git a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
index f39fa6ac8829c4..69dde3c313dfec 100644
--- a/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
+++ b/llvm/lib/Target/LoongArch/LoongArchInstrInfo.td
@@ -533,55 +533,55 @@ include "LoongArchLASXInstrFormats.td"
//===----------------------------------------------------------------------===//
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-class ALU_3R<bits<17> op>
+class ALU_3R<bits<32> op>
: Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), "$rd, $rj, $rk">;
-class ALU_2R<bits<22> op>
+class ALU_2R<bits<32> op>
: Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), "$rd, $rj">;
-class ALU_3RI2<bits<15> op, Operand ImmOpnd>
+class ALU_3RI2<bits<32> op, Operand ImmOpnd>
: Fmt3RI2<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm2),
"$rd, $rj, $rk, $imm2">;
-class ALU_3RI3<bits<14> op, Operand ImmOpnd>
+class ALU_3RI3<bits<32> op, Operand ImmOpnd>
: Fmt3RI3<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk, ImmOpnd:$imm3),
"$rd, $rj, $rk, $imm3">;
-class ALU_2RI5<bits<17> op, Operand ImmOpnd>
+class ALU_2RI5<bits<32> op, Operand ImmOpnd>
: Fmt2RI5<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm5),
"$rd, $rj, $imm5">;
-class ALU_2RI6<bits<16> op, Operand ImmOpnd>
+class ALU_2RI6<bits<32> op, Operand ImmOpnd>
: Fmt2RI6<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm6),
"$rd, $rj, $imm6">;
-class ALU_2RI12<bits<10> op, Operand ImmOpnd>
+class ALU_2RI12<bits<32> op, Operand ImmOpnd>
: Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm12),
"$rd, $rj, $imm12">;
-class ALU_2RI16<bits<6> op, Operand ImmOpnd>
+class ALU_2RI16<bits<32> op, Operand ImmOpnd>
: Fmt2RI16<op, (outs GPR:$rd), (ins GPR:$rj, ImmOpnd:$imm16),
"$rd, $rj, $imm16">;
-class ALU_1RI20<bits<7> op, Operand ImmOpnd>
+class ALU_1RI20<bits<32> op, Operand ImmOpnd>
: Fmt1RI20<op, (outs GPR:$rd), (ins ImmOpnd:$imm20), "$rd, $imm20">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
-class MISC_I15<bits<17> op>
+class MISC_I15<bits<32> op>
: FmtI15<op, (outs), (ins uimm15:$imm15), "$imm15">;
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
-class RDTIME_2R<bits<22> op>
+class RDTIME_2R<bits<32> op>
: Fmt2R<op, (outs GPR:$rd, GPR:$rj), (ins), "$rd, $rj">;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in {
-class BrCC_2RI16<bits<6> op>
+class BrCC_2RI16<bits<32> op>
: Fmt2RI16<op, (outs), (ins GPR:$rj, GPR:$rd, simm16_lsl2_br:$imm16),
"$rj, $rd, $imm16"> {
let isBranch = 1;
let isTerminator = 1;
}
-class BrCCZ_1RI21<bits<6> op>
+class BrCCZ_1RI21<bits<32> op>
: Fmt1RI21<op, (outs), (ins GPR:$rj, simm21_lsl2:$imm21),
"$rj, $imm21"> {
let isBranch = 1;
let isTerminator = 1;
}
-class Br_I26<bits<6> op>
+class Br_I26<bits<32> op>
: FmtI26<op, (outs), (ins simm26_b:$imm26), "$imm26"> {
let isBranch = 1;
let isTerminator = 1;
@@ -589,49 +589,49 @@ class Br_I26<bits<6> op>
} // hasSideEffects = 0, mayLoad = 0, mayStore = 0
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in {
-class LOAD_3R<bits<17> op>
+class LOAD_3R<bits<32> op>
: Fmt3R<op, (outs GPR:$rd), (ins GPR:$rj, GPR:$rk), "$rd, $rj, $rk">;
-class LOAD_2RI12<bits<10> op>
+class LOAD_2RI12<bits<32> op>
: Fmt2RI12<op, (outs GPR:$rd), (ins GPR:$rj, simm12_addlike:$imm12),
"$rd, $rj, $imm12">;
-class LOAD_2RI14<bits<8> op>
+class LOAD_2RI14<bits<32> op>
: Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14),
"$rd, $rj, $imm14">;
} // hasSideEffects = 0, mayLoad = 1, mayStore = 0
let hasSideEffects = 0, mayLoad = 0, mayStore = 1 in {
-class STORE_3R<bits<17> op>
+class STORE_3R<bits<32> op>
: Fmt3R<op, (outs), (ins GPR:$rd, GPR:$rj, GPR:$rk),
"$rd, $rj, $rk">;
-class STORE_2RI12<bits<10> op>
+class STORE_2RI12<bits<32> op>
: Fmt2RI12<op, (outs), (ins GPR:$rd, GPR:$rj, simm12_addlike:$imm12),
"$rd, $rj, $imm12">;
-class STORE_2RI14<bits<8> op>
+class STORE_2RI14<bits<32> op>
: Fmt2RI14<op, (outs), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14),
"$rd, $rj, $imm14">;
} // hasSideEffects = 0, mayLoad = 0, mayStore = 1
let hasSideEffects = 0, mayLoad = 1, mayStore = 1, Constraints = "@earlyclobber $rd" in
-class AM_3R<bits<17> op>
+class AM_3R<bits<32> op>
: Fmt3R<op, (outs GPR:$rd), (ins GPR:$rk, GPRMemAtomic:$rj),
"$rd, $rk, $rj">;
let hasSideEffects = 0, mayLoad = 1, mayStore = 0 in
-class LLBase<bits<8> op>
+class LLBase<bits<32> op>
: Fmt2RI14<op, (outs GPR:$rd), (ins GPR:$rj, simm14_lsl2:$imm14),
"$rd, $rj, $imm14">;
let hasSideEffects = 0, mayLoad = 0, mayStore = 1, Constraints = "$rd = $dst" in
-class SCBase<bits<8> op>
+class SCBase<bits<32> op>
: Fmt2RI14<op, (outs GPR:$dst), (ins GPR:$rd, GPR:$rj, simm14_lsl2:$imm14),
"$rd, $rj, $imm14">;
let hasSideEffects = 1 in
-class IOCSRRD<bits<22> op>
+class IOCSRRD<bits<32> op>
: Fmt2R<op, (outs GPR:$rd), (ins GPR:$rj), "$rd, $rj">;
let hasSideEffects = 1 in
-class IOCSRWR<bits<22> op>
+class IOCSRWR<bits<32> op>
: Fmt2R<op, (outs), (ins GPR:$rd, GPR:$rj), "$rd, $rj">;
//===----------------------------------------------------------------------===//
@@ -639,114 +639,114 @@ class IOCSRWR<bits<22> op>
//===----------------------------------------------------------------------===//
// Arithmetic Operation Instructions
-def ADD_W : ALU_3R<0b00000000000100000>;
-def SUB_W : ALU_3R<0b00000000000100010>;
-def ADDI_W : ALU_2RI12<0b0000001010, simm12_addlike>;
-def ALSL_W : ALU_3RI2<0b000000000000010, uimm2_plus1>;
-def LU12I_W : ALU_1RI20<0b0001010, simm20_lu12iw>;
-def SLT : ALU_3R<0b00000000000100100>;
-def SLTU : ALU_3R<0b00000000000100101>;
-def SLTI : ALU_2RI12<0b0000001000, simm12>;
-def SLTUI : ALU_2RI12<0b0000001001, simm12>;
-def PCADDI : ALU_1RI20<0b0001100, simm20>;
-def PCADDU12I : ALU_1RI20<0b0001110, simm20>;
-def PCALAU12I : ALU_1RI20<0b0001101, simm20_pcalau12i>;
-def AND : ALU_3R<0b00000000000101001>;
-def OR : ALU_3R<0b00000000000101010>;
-def NOR : ALU_3R<0b00000000000101000>;
-def XOR : ALU_3R<0b00000000000101011>;
-def ANDN : ALU_3R<0b00000000000101101>;
-def ORN : ALU_3R<0b00000000000101100>;
-def ANDI : ALU_2RI12<0b0000001101, uimm12>;
-def ORI : ALU_2RI12<0b0000001110, uimm12_ori>;
-def XORI : ALU_2RI12<0b0000001111, uimm12>;
-def MUL_W : ALU_3R<0b00000000000111000>;
-def MULH_W : ALU_3R<0b00000000000111001>;
-def MULH_WU : ALU_3R<0b00000000000111010>;
+def ADD_W : ALU_3R<0x00100000>;
+def SUB_W : ALU_3R<0x00110000>;
+def ADDI_W : ALU_2RI12<0x02800000, simm12_addlike>;
+def ALSL_W : ALU_3RI2<0x00040000, uimm2_plus1>;
+def LU12I_W : ALU_1RI20<0x14000000, simm20_lu12iw>;
+def SLT : ALU_3R<0x00120000>;
+def SLTU : ALU_3R<0x00128000>;
+def SLTI : ALU_2RI12<0x02000000, simm12>;
+def SLTUI : ALU_2RI12<0x02400000, simm12>;
+def PCADDI : ALU_1RI20<0x18000000, simm20>;
+def PCADDU12I : ALU_1RI20<0x1c000000, simm20>;
+def PCALAU12I : ALU_1RI20<0x1a000000, simm20_pcalau12i>;
+def AND : ALU_3R<0x00148000>;
+def OR : ALU_3R<0x00150000>;
+def NOR : ALU_3R<0x00140000>;
+def XOR : ALU_3R<0x00158000>;
+def ANDN : ALU_3R<0x00168000>;
+def ORN : ALU_3R<0x00160000>;
+def ANDI : ALU_2RI12<0x03400000, uimm12>;
+def ORI : ALU_2RI12<0x03800000, uimm12_ori>;
+def XORI : ALU_2RI12<0x03c00000, uimm12>;
+def MUL_W : ALU_3R<0x001c0000>;
+def MULH_W : ALU_3R<0x001c8000>;
+def MULH_WU : ALU_3R<0x001d0000>;
let usesCustomInserter = true in {
-def DIV_W : ALU_3R<0b00000000001000000>;
-def MOD_W : ALU_3R<0b00000000001000001>;
-def DIV_WU : ALU_3R<0b00000000001000010>;
-def MOD_WU : ALU_3R<0b00000000001000011>;
+def DIV_W : ALU_3R<0x00200000>;
+def MOD_W : ALU_3R<0x00208000>;
+def DIV_WU : ALU_3R<0x00210000>;
+def MOD_WU : ALU_3R<0x00218000>;
} // usesCustomInserter = true
// Bit-shift Instructions
-def SLL_W : ALU_3R<0b00000000000101110>;
-def SRL_W : ALU_3R<0b00000000000101111>;
-def SRA_W : ALU_3R<0b00000000000110000>;
-def ROTR_W : ALU_3R<0b00000000000110110>;
+def SLL_W : ALU_3R<0x00170000>;
+def SRL_W : ALU_3R<0x00178000>;
+def SRA_W : ALU_3R<0x00180000>;
+def ROTR_W : ALU_3R<0x001b0000>;
-def SLLI_W : ALU_2RI5<0b00000000010000001, uimm5>;
-def SRLI_W : ALU_2RI5<0b00000000010001001, uimm5>;
-def SRAI_W : ALU_2RI5<0b00000000010010001, uimm5>;
-def ROTRI_W : ALU_2RI5<0b00000000010011001, uimm5>;
+def SLLI_W : ALU_2RI5<0x00408000, uimm5>;
+def SRLI_W : ALU_2RI5<0x00448000, uimm5>;
+def SRAI_W : ALU_2RI5<0x00488000, uimm5>;
+def ROTRI_W : ALU_2RI5<0x004c8000, uimm5>;
// Bit-manipulation Instructions
-def EXT_W_B : ALU_2R<0b0000000000000000010111>;
-def EXT_W_H : ALU_2R<0b0000000000000000010110>;
-def CLO_W : ALU_2R<0b0000000000000000000100>;
-def CLZ_W : ALU_2R<0b0000000000000000000101>;
-def CTO_W : ALU_2R<0b0000000000000000000110>;
-def CTZ_W : ALU_2R<0b0000000000000000000111>;
-def BYTEPICK_W : ALU_3RI2<0b000000000000100, uimm2>;
-def REVB_2H : ALU_2R<0b0000000000000000001100>;
-def BITREV_4B : ALU_2R<0b0000000000000000010010>;
-def BITREV_W : ALU_2R<0b0000000000000000010100>;
+def EXT_W_B : ALU_2R<0x00005c00>;
+def EXT_W_H : ALU_2R<0x00005800>;
+def CLO_W : ALU_2R<0x00001000>;
+def CLZ_W : ALU_2R<0x00001400>;
+def CTO_W : ALU_2R<0x00001800>;
+def CTZ_W : ALU_2R<0x00001c00>;
+def BYTEPICK_W : ALU_3RI2<0x00080000, uimm2>;
+def REVB_2H : ALU_2R<0x00003000>;
+def BITREV_4B : ALU_2R<0x00004800>;
+def BITREV_W : ALU_2R<0x00005000>;
let Constraints = "$rd = $dst" in {
-def BSTRINS_W : FmtBSTR_W<0b000000000110, (outs GPR:$dst),
+def BSTRINS_W : FmtBSTR_W<0x00600000, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
"$rd, $rj, $msbw, $lsbw">;
}
-def BSTRPICK_W : FmtBSTR_W<0b000000000111, (outs GPR:$rd),
+def BSTRPICK_W : FmtBSTR_W<0x00608000, (outs GPR:$rd),
(ins GPR:$rj, uimm5:$msbw, uimm5:$lsbw),
"$rd, $rj, $msbw, $lsbw">;
-def MASKEQZ : ALU_3R<0b00000000000100110>;
-def MASKNEZ : ALU_3R<0b00000000000100111>;
+def MASKEQZ : ALU_3R<0x00130000>;
+def MASKNEZ : ALU_3R<0x00138000>;
// Branch Instructions
-def BEQ : BrCC_2RI16<0b010110>;
-def BNE : BrCC_2RI16<0b010111>;
-def BLT : BrCC_2RI16<0b011000>;
-def BGE : BrCC_2RI16<0b011001>;
-def BLTU : BrCC_2RI16<0b011010>;
-def BGEU : BrCC_2RI16<0b011011>;
-def BEQZ : BrCCZ_1RI21<0b010000>;
-def BNEZ : BrCCZ_1RI21<0b010001>;
-def B : Br_I26<0b010100>;
+def BEQ : BrCC_2RI16<0x58000000>;
+def BNE : BrCC_2RI16<0x5c000000>;
+def BLT : BrCC_2RI16<0x60000000>;
+def BGE : BrCC_2RI16<0x64000000>;
+def BLTU : BrCC_2RI16<0x68000000>;
+def BGEU : BrCC_2RI16<0x6c000000>;
+def BEQZ : BrCCZ_1RI21<0x40000000>;
+def BNEZ : BrCCZ_1RI21<0x44000000>;
+def B : Br_I26<0x50000000>;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCall = 1, Defs=[R1] in
-def BL : FmtI26<0b010101, (outs), (ins simm26_symbol:$imm26), "$imm26">;
+def BL : FmtI26<0x54000000, (outs), (ins simm26_symbol:$imm26), "$imm26">;
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def JIRL : Fmt2RI16<0b010011, (outs GPR:$rd),
+def JIRL : Fmt2RI16<0x4c000000, (outs GPR:$rd),
(ins GPR:$rj, simm16_lsl2:$imm16), "$rd, $rj, $imm16">;
// Common Memory Access Instructions
-def LD_B : LOAD_2RI12<0b0010100000>;
-def LD_H : LOAD_2RI12<0b0010100001>;
-def LD_W : LOAD_2RI12<0b0010100010>;
-def LD_BU : LOAD_2RI12<0b0010101000>;
-def LD_HU : LOAD_2RI12<0b0010101001>;
-def ST_B : STORE_2RI12<0b0010100100>;
-def ST_H : STORE_2RI12<0b0010100101>;
-def ST_W : STORE_2RI12<0b0010100110>;
+def LD_B : LOAD_2RI12<0x28000000>;
+def LD_H : LOAD_2RI12<0x28400000>;
+def LD_W : LOAD_2RI12<0x28800000>;
+def LD_BU : LOAD_2RI12<0x2a000000>;
+def LD_HU : LOAD_2RI12<0x2a400000>;
+def ST_B : STORE_2RI12<0x29000000>;
+def ST_H : STORE_2RI12<0x29400000>;
+def ST_W : STORE_2RI12<0x29800000>;
let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
def PRELD : FmtPRELD<(outs), (ins uimm5:$imm5, GPR:$rj, simm12:$imm12),
"$imm5, $rj, $imm12">;
// Atomic Memory Access Instructions
-def LL_W : LLBase<0b00100000>;
-def SC_W : SCBase<0b00100001>;
+def LL_W : LLBase<0x20000000>;
+def SC_W : SCBase<0x21000000>;
// Barrier Instructions
-def DBAR : MISC_I15<0b00111000011100100>;
-def IBAR : MISC_I15<0b00111000011100101>;
+def DBAR : MISC_I15<0x38720000>;
+def IBAR : MISC_I15<0x38728000>;
// Other Miscellaneous Instructions
-def SYSCALL : MISC_I15<0b00000000001010110>;
-def BREAK : MISC_I15<0b00000000001010100>;
-def RDTIMEL_W : RDTIME_2R<0b0000000000000000011000>;
-def RDTIMEH_W : RDTIME_2R<0b0000000000000000011001>;
-def CPUCFG : ALU_2R<0b0000000000000000011011>;
+def SYSCALL : MISC_I15<0x002b0000>;
+def BREAK : MISC_I15<0x002a0000>;
+def RDTIMEL_W : RDTIME_2R<0x00006000>;
+def RDTIMEH_W : RDTIME_2R<0x00006400>;
+def CPUCFG : ALU_2R<0x00006c00>;
// Cache Maintenance Instructions
def CACOP : FmtCACOP<(outs), (ins uimm5:$op, GPR:$rj, simm12:$imm12),
@@ -757,161 +757,161 @@ def CACOP : FmtCACOP<(outs), (ins uimm5:$op, GPR:$rj, simm12:$imm12),
let Predicates = [IsLA64] in {
// Arithmetic Operation Instructions for 64-bits
-def ADD_D : ALU_3R<0b00000000000100001>;
-def SUB_D : ALU_3R<0b00000000000100011>;
-def ADDI_D : ALU_2RI12<0b0000001011, simm12_addlike>;
-def ADDU16I_D : ALU_2RI16<0b000100, simm16>;
-def ALSL_WU : ALU_3RI2<0b000000000000011, uimm2_plus1>;
-def ALSL_D : ALU_3RI2<0b000000000010110, uimm2_plus1>;
+def ADD_D : ALU_3R<0x00108000>;
+def SUB_D : ALU_3R<0x00118000>;
+def ADDI_D : ALU_2RI12<0x02c00000, simm12_addlike>;
+def ADDU16I_D : ALU_2RI16<0x10000000, simm16>;
+def ALSL_WU : ALU_3RI2<0x00060000, uimm2_plus1>;
+def ALSL_D : ALU_3RI2<0x002c0000, uimm2_plus1>;
let Constraints = "$rd = $dst" in {
let hasSideEffects = 0, mayLoad = 0, mayStore = 0 in
-def LU32I_D : Fmt1RI20<0b0001011, (outs GPR:$dst),
+def LU32I_D : Fmt1RI20<0x16000000, (outs GPR:$dst),
(ins GPR:$rd, simm20_lu32id:$imm20),
"$rd, $imm20">;
}
-def LU52I_D : ALU_2RI12<0b0000001100, simm12_lu52id>;
-def PCADDU18I : ALU_1RI20<0b0001111, simm20>;
-def MUL_D : ALU_3R<0b00000000000111011>;
-def MULH_D : ALU_3R<0b00000000000111100>;
-def MULH_DU : ALU_3R<0b00000000000111101>;
-def MULW_D_W : ALU_3R<0b00000000000111110>;
-def MULW_D_WU : ALU_3R<0b00000000000111111>;
+def LU52I_D : ALU_2RI12<0x03000000, simm12_lu52id>;
+def PCADDU18I : ALU_1RI20<0x1e000000, simm20>;
+def MUL_D : ALU_3R<0x001d8000>;
+def MULH_D : ALU_3R<0x001e0000>;
+def MULH_DU : ALU_3R<0x001e8000>;
+def MULW_D_W : ALU_3R<0x001f0000>;
+def MULW_D_WU : ALU_3R<0x001f8000>;
let usesCustomInserter = true in {
-def DIV_D : ALU_3R<0b00000000001000100>;
-def MOD_D : ALU_3R<0b00000000001000101>;
-def DIV_DU : ALU_3R<0b00000000001000110>;
-def MOD_DU : ALU_3R<0b00000000001000111>;
+def DIV_D : ALU_3R<0x00220000>;
+def MOD_D : ALU_3R<0x00228000>;
+def DIV_DU : ALU_3R<0x00230000>;
+def MOD_DU : ALU_3R<0x00238000>;
} // usesCustomInserter = true
// Bit-shift Instructions for 64-bits
-def SLL_D : ALU_3R<0b00000000000110001>;
-def SRL_D : ALU_3R<0b00000000000110010>;
-def SRA_D : ALU_3R<0b00000000000110011>;
-def ROTR_D : ALU_3R<0b00000000000110111>;
-def SLLI_D : ALU_2RI6<0b0000000001000001, uimm6>;
-def SRLI_D : ALU_2RI6<0b0000000001000101, uimm6>;
-def SRAI_D : ALU_2RI6<0b0000000001001001, uimm6>;
-def ROTRI_D : ALU_2RI6<0b0000000001001101, uimm6>;
+def SLL_D : ALU_3R<0x00188000>;
+def SRL_D : ALU_3R<0x00190000>;
+def SRA_D : ALU_3R<0x00198000>;
+def ROTR_D : ALU_3R<0x001b8000>;
+def SLLI_D : ALU_2RI6<0x00410000, uimm6>;
+def SRLI_D : ALU_2RI6<0x00450000, uimm6>;
+def SRAI_D : ALU_2RI6<0x00490000, uimm6>;
+def ROTRI_D : ALU_2RI6<0x004d0000, uimm6>;
// Bit-manipulation Instructions for 64-bits
-def CLO_D : ALU_2R<0b0000000000000000001000>;
-def CLZ_D : ALU_2R<0b0000000000000000001001>;
-def CTO_D : ALU_2R<0b0000000000000000001010>;
-def CTZ_D : ALU_2R<0b0000000000000000001011>;
-def BYTEPICK_D : ALU_3RI3<0b00000000000011, uimm3>;
-def REVB_4H : ALU_2R<0b0000000000000000001101>;
-def REVB_2W : ALU_2R<0b0000000000000000001110>;
-def REVB_D : ALU_2R<0b0000000000000000001111>;
-def REVH_2W : ALU_2R<0b0000000000000000010000>;
-def REVH_D : ALU_2R<0b0000000000000000010001>;
-def BITREV_8B : ALU_2R<0b0000000000000000010011>;
-def BITREV_D : ALU_2R<0b0000000000000000010101>;
+def CLO_D : ALU_2R<0x00002000>;
+def CLZ_D : ALU_2R<0x00002400>;
+def CTO_D : ALU_2R<0x00002800>;
+def CTZ_D : ALU_2R<0x00002c00>;
+def BYTEPICK_D : ALU_3RI3<0x000c0000, uimm3>;
+def REVB_4H : ALU_2R<0x00003400>;
+def REVB_2W : ALU_2R<0x00003800>;
+def REVB_D : ALU_2R<0x00003c00>;
+def REVH_2W : ALU_2R<0x00004000>;
+def REVH_D : ALU_2R<0x00004400>;
+def BITREV_8B : ALU_2R<0x00004c00>;
+def BITREV_D : ALU_2R<0x00005400>;
let Constraints = "$rd = $dst" in {
-def BSTRINS_D : FmtBSTR_D<0b0000000010, (outs GPR:$dst),
+def BSTRINS_D : FmtBSTR_D<0x00800000, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
"$rd, $rj, $msbd, $lsbd">;
}
-def BSTRPICK_D : FmtBSTR_D<0b0000000011, (outs GPR:$rd),
+def BSTRPICK_D : FmtBSTR_D<0x00c00000, (outs GPR:$rd),
(ins GPR:$rj, uimm6:$msbd, uimm6:$lsbd),
"$rd, $rj, $msbd, $lsbd">;
// Common Memory Access Instructions for 64-bits
-def LD_WU : LOAD_2RI12<0b0010101010>;
-def LD_D : LOAD_2RI12<0b0010100011>;
-def ST_D : STORE_2RI12<0b0010100111>;
-def LDX_B : LOAD_3R<0b00111000000000000>;
-def LDX_H : LOAD_3R<0b00111000000001000>;
-def LDX_W : LOAD_3R<0b00111000000010000>;
-def LDX_D : LOAD_3R<0b00111000000011000>;
-def LDX_BU : LOAD_3R<0b00111000001000000>;
-def LDX_HU : LOAD_3R<0b00111000001001000>;
-def LDX_WU : LOAD_3R<0b00111000001010000>;
-def STX_B : STORE_3R<0b00111000000100000>;
-def STX_H : STORE_3R<0b00111000000101000>;
-def STX_W : STORE_3R<0b00111000000110000>;
-def STX_D : STORE_3R<0b00111000000111000>;
-def LDPTR_W : LOAD_2RI14<0b00100100>;
-def LDPTR_D : LOAD_2RI14<0b00100110>;
-def STPTR_W : STORE_2RI14<0b00100101>;
-def STPTR_D : STORE_2RI14<0b00100111>;
+def LD_WU : LOAD_2RI12<0x2a800000>;
+def LD_D : LOAD_2RI12<0x28c00000>;
+def ST_D : STORE_2RI12<0x29c00000>;
+def LDX_B : LOAD_3R<0x38000000>;
+def LDX_H : LOAD_3R<0x38040000>;
+def LDX_W : LOAD_3R<0x38080000>;
+def LDX_D : LOAD_3R<0x380c0000>;
+def LDX_BU : LOAD_3R<0x38200000>;
+def LDX_HU : LOAD_3R<0x38240000>;
+def LDX_WU : LOAD_3R<0x38280000>;
+def STX_B : STORE_3R<0x38100000>;
+def STX_H : STORE_3R<0x38140000>;
+def STX_W : STORE_3R<0x38180000>;
+def STX_D : STORE_3R<0x381c0000>;
+def LDPTR_W : LOAD_2RI14<0x24000000>;
+def LDPTR_D : LOAD_2RI14<0x26000000>;
+def STPTR_W : STORE_2RI14<0x25000000>;
+def STPTR_D : STORE_2RI14<0x27000000>;
let hasSideEffects = 0, mayLoad = 1, mayStore = 1 in
def PRELDX : FmtPRELDX<(outs), (ins uimm5:$imm5, GPR:$rj, GPR:$rk),
"$imm5, $rj, $rk">;
// Bound Check Memory Access Instructions
-def LDGT_B : LOAD_3R<0b00111000011110000>;
-def LDGT_H : LOAD_3R<0b00111000011110001>;
-def LDGT_W : LOAD_3R<0b00111000011110010>;
-def LDGT_D : LOAD_3R<0b00111000011110011>;
-def LDLE_B : LOAD_3R<0b00111000011110100>;
-def LDLE_H : LOAD_3R<0b00111000011110101>;
-def LDLE_W : LOAD_3R<0b00111000011110110>;
-def LDLE_D : LOAD_3R<0b00111000011110111>;
-def STGT_B : STORE_3R<0b00111000011111000>;
-def STGT_H : STORE_3R<0b00111000011111001>;
-def STGT_W : STORE_3R<0b00111000011111010>;
-def STGT_D : STORE_3R<0b00111000011111011>;
-def STLE_B : STORE_3R<0b00111000011111100>;
-def STLE_H : STORE_3R<0b00111000011111101>;
-def STLE_W : STORE_3R<0b00111000011111110>;
-def STLE_D : STORE_3R<0b00111000011111111>;
+def LDGT_B : LOAD_3R<0x38780000>;
+def LDGT_H : LOAD_3R<0x38788000>;
+def LDGT_W : LOAD_3R<0x38790000>;
+def LDGT_D : LOAD_3R<0x38798000>;
+def LDLE_B : LOAD_3R<0x387a0000>;
+def LDLE_H : LOAD_3R<0x387a8000>;
+def LDLE_W : LOAD_3R<0x387b0000>;
+def LDLE_D : LOAD_3R<0x387b8000>;
+def STGT_B : STORE_3R<0x387c0000>;
+def STGT_H : STORE_3R<0x387c8000>;
+def STGT_W : STORE_3R<0x387d0000>;
+def STGT_D : STORE_3R<0x387d8000>;
+def STLE_B : STORE_3R<0x387e0000>;
+def STLE_H : STORE_3R<0x387e8000>;
+def STLE_W : STORE_3R<0x387f0000>;
+def STLE_D : STORE_3R<0x387f8000>;
// Atomic Memory Access Instructions for 64-bits
-def AMSWAP_W : AM_3R<0b00111000011000000>;
-def AMSWAP_D : AM_3R<0b00111000011000001>;
-def AMADD_W : AM_3R<0b00111000011000010>;
-def AMADD_D : AM_3R<0b00111000011000011>;
-def AMAND_W : AM_3R<0b00111000011000100>;
-def AMAND_D : AM_3R<0b00111000011000101>;
-def AMOR_W : AM_3R<0b00111000011000110>;
-def AMOR_D : AM_3R<0b00111000011000111>;
-def AMXOR_W : AM_3R<0b00111000011001000>;
-def AMXOR_D : AM_3R<0b00111000011001001>;
-def AMMAX_W : AM_3R<0b00111000011001010>;
-def AMMAX_D : AM_3R<0b00111000011001011>;
-def AMMIN_W : AM_3R<0b00111000011001100>;
-def AMMIN_D : AM_3R<0b00111000011001101>;
-def AMMAX_WU : AM_3R<0b00111000011001110>;
-def AMMAX_DU : AM_3R<0b00111000011001111>;
-def AMMIN_WU : AM_3R<0b00111000011010000>;
-def AMMIN_DU : AM_3R<0b00111000011010001>;
-def AMSWAP__DB_W : AM_3R<0b00111000011010010>;
-def AMSWAP__DB_D : AM_3R<0b00111000011010011>;
-def AMADD__DB_W : AM_3R<0b00111000011010100>;
-def AMADD__DB_D : AM_3R<0b00111000011010101>;
-def AMAND__DB_W : AM_3R<0b00111000011010110>;
-def AMAND__DB_D : AM_3R<0b00111000011010111>;
-def AMOR__DB_W : AM_3R<0b00111000011011000>;
-def AMOR__DB_D : AM_3R<0b00111000011011001>;
-def AMXOR__DB_W : AM_3R<0b00111000011011010>;
-def AMXOR__DB_D : AM_3R<0b00111000011011011>;
-def AMMAX__DB_W : AM_3R<0b00111000011011100>;
-def AMMAX__DB_D : AM_3R<0b00111000011011101>;
-def AMMIN__DB_W : AM_3R<0b00111000011011110>;
-def AMMIN__DB_D : AM_3R<0b00111000011011111>;
-def AMMAX__DB_WU : AM_3R<0b00111000011100000>;
-def AMMAX__DB_DU : AM_3R<0b00111000011100001>;
-def AMMIN__DB_WU : AM_3R<0b00111000011100010>;
-def AMMIN__DB_DU : AM_3R<0b00111000011100011>;
-def LL_D : LLBase<0b00100010>;
-def SC_D : SCBase<0b00100011>;
+def AMSWAP_W : AM_3R<0x38600000>;
+def AMSWAP_D : AM_3R<0x38608000>;
+def AMADD_W : AM_3R<0x38610000>;
+def AMADD_D : AM_3R<0x38618000>;
+def AMAND_W : AM_3R<0x38620000>;
+def AMAND_D : AM_3R<0x38628000>;
+def AMOR_W : AM_3R<0x38630000>;
+def AMOR_D : AM_3R<0x38638000>;
+def AMXOR_W : AM_3R<0x38640000>;
+def AMXOR_D : AM_3R<0x38648000>;
+def AMMAX_W : AM_3R<0x38650000>;
+def AMMAX_D : AM_3R<0x38658000>;
+def AMMIN_W : AM_3R<0x38660000>;
+def AMMIN_D : AM_3R<0x38668000>;
+def AMMAX_WU : AM_3R<0x38670000>;
+def AMMAX_DU : AM_3R<0x38678000>;
+def AMMIN_WU : AM_3R<0x38680000>;
+def AMMIN_DU : AM_3R<0x38688000>;
+def AMSWAP__DB_W : AM_3R<0x38690000>;
+def AMSWAP__DB_D : AM_3R<0x38698000>;
+def AMADD__DB_W : AM_3R<0x386a0000>;
+def AMADD__DB_D : AM_3R<0x386a8000>;
+def AMAND__DB_W : AM_3R<0x386b0000>;
+def AMAND__DB_D : AM_3R<0x386b8000>;
+def AMOR__DB_W : AM_3R<0x386c0000>;
+def AMOR__DB_D : AM_3R<0x386c8000>;
+def AMXOR__DB_W : AM_3R<0x386d0000>;
+def AMXOR__DB_D : AM_3R<0x386d8000>;
+def AMMAX__DB_W : AM_3R<0x386e0000>;
+def AMMAX__DB_D : AM_3R<0x386e8000>;
+def AMMIN__DB_W : AM_3R<0x386f0000>;
+def AMMIN__DB_D : AM_3R<0x386f8000>;
+def AMMAX__DB_WU : AM_3R<0x38700000>;
+def AMMAX__DB_DU : AM_3R<0x38708000>;
+def AMMIN__DB_WU : AM_3R<0x38710000>;
+def AMMIN__DB_DU : AM_3R<0x38718000>;
+def LL_D : LLBase<0x22000000>;
+def SC_D : SCBase<0x23000000>;
// CRC Check Instructions
-def CRC_W_B_W : ALU_3R<0b00000000001001000>;
-def CRC_W_H_W : ALU_3R<0b00000000001001001>;
-def CRC_W_W_W : ALU_3R<0b00000000001001010>;
-def CRC_W_D_W : ALU_3R<0b00000000001001011>;
-def CRCC_W_B_W : ALU_3R<0b00000000001001100>;
-def CRCC_W_H_W : ALU_3R<0b00000000001001101>;
-def CRCC_W_W_W : ALU_3R<0b00000000001001110>;
-def CRCC_W_D_W : ALU_3R<0b00000000001001111>;
+def CRC_W_B_W : ALU_3R<0x00240000>;
+def CRC_W_H_W : ALU_3R<0x00248000>;
+def CRC_W_W_W : ALU_3R<0x00250000>;
+def CRC_W_D_W : ALU_3R<0x00258000>;
+def CRCC_W_B_W : ALU_3R<0x00260000>;
+def CRCC_W_H_W : ALU_3R<0x00268000>;
+def CRCC_W_W_W : ALU_3R<0x00270000>;
+def CRCC_W_D_W : ALU_3R<0x00278000>;
// Other Miscellaneous Instructions for 64-bits
-def ASRTLE_D : FmtASRT<0b00000000000000010, (outs), (ins GPR:$rj, GPR:$rk),
+def ASRTLE_D : FmtASRT<0x00010000, (outs), (ins GPR:$rj, GPR:$rk),
"$rj, $rk">;
-def ASRTGT_D : FmtASRT<0b00000000000000011, (outs), (ins GPR:$rj, GPR:$rk),
+def ASRTGT_D : FmtASRT<0x00018000, (outs), (ins GPR:$rj, GPR:$rk),
"$rj, $rk">;
-def RDTIME_D : RDTIME_2R<0b0000000000000000011010>;
+def RDTIME_D : RDTIME_2R<0x00006800>;
} // Predicates = [IsLA64]
//===----------------------------------------------------------------------===//
@@ -1948,51 +1948,51 @@ let Predicates = [HasBasicF], usesCustomInserter = 1 in {
// CSR Access Instructions
let hasSideEffects = 1 in
-def CSRRD : FmtCSR<0b0000010000000, (outs GPR:$rd), (ins uimm14:$csr_num),
+def CSRRD : FmtCSR<0x04000000, (outs GPR:$rd), (ins uimm14:$csr_num),
"$rd, $csr_num">;
let hasSideEffects = 1, Constraints = "$rd = $dst" in {
-def CSRWR : FmtCSR<0b0000010000001, (outs GPR:$dst),
+def CSRWR : FmtCSR<0x04000020, (outs GPR:$dst),
(ins GPR:$rd, uimm14:$csr_num), "$rd, $csr_num">;
-def CSRXCHG : FmtCSRXCHG<0b00000100, (outs GPR:$dst),
+def CSRXCHG : FmtCSRXCHG<0x04000000, (outs GPR:$dst),
(ins GPR:$rd, GPR:$rj, uimm14:$csr_num),
"$rd, $rj, $csr_num">;
} // hasSideEffects = 1, Constraints = "$rd = $dst"
// IOCSR Access Instructions
-def IOCSRRD_B : IOCSRRD<0b0000011001001000000000>;
-def IOCSRRD_H : IOCSRRD<0b0000011001001000000001>;
-def IOCSRRD_W : IOCSRRD<0b0000011001001000000010>;
-def IOCSRWR_B : IOCSRWR<0b0000011001001000000100>;
-def IOCSRWR_H : IOCSRWR<0b0000011001001000000101>;
-def IOCSRWR_W : IOCSRWR<0b0000011001001000000110>;
+def IOCSRRD_B : IOCSRRD<0x06480000>;
+def IOCSRRD_H : IOCSRRD<0x06480400>;
+def IOCSRRD_W : IOCSRRD<0x06480800>;
+def IOCSRWR_B : IOCSRWR<0x06481000>;
+def IOCSRWR_H : IOCSRWR<0x06481400>;
+def IOCSRWR_W : IOCSRWR<0x06481800>;
let Predicates = [IsLA64] in {
-def IOCSRRD_D : IOCSRRD<0b0000011001001000000011>;
-def IOCSRWR_D : IOCSRWR<0b0000011001001000000111>;
+def IOCSRRD_D : IOCSRRD<0x06480c00>;
+def IOCSRWR_D : IOCSRWR<0x06481c00>;
} // Predicates = [IsLA64]
// TLB Maintenance Instructions
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in {
-def TLBSRCH : FmtI32<0b00000110010010000010100000000000>;
-def TLBRD : FmtI32<0b00000110010010000010110000000000>;
-def TLBWR : FmtI32<0b00000110010010000011000000000000>;
-def TLBFILL : FmtI32<0b00000110010010000011010000000000>;
-def TLBCLR : FmtI32<0b00000110010010000010000000000000>;
-def TLBFLUSH : FmtI32<0b00000110010010000010010000000000>;
+def TLBSRCH : FmtI32<0x06482800>;
+def TLBRD : FmtI32<0x06482c00>;
+def TLBWR : FmtI32<0x06483000>;
+def TLBFILL : FmtI32<0x06483400>;
+def TLBCLR : FmtI32<0x06482000>;
+def TLBFLUSH : FmtI32<0x06482400>;
def INVTLB : FmtINVTLB<(outs), (ins GPR:$rk, GPR:$rj, uimm5:$op),
"$op, $rj, $rk">;
} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
// Software Page Walking Instructions
-def LDDIR : Fmt2RI8<0b00000110010000, (outs GPR:$rd),
+def LDDIR : Fmt2RI8<0x06400000, (outs GPR:$rd),
(ins GPR:$rj, uimm8:$imm8), "$rd, $rj, $imm8">;
def LDPTE : FmtLDPTE<(outs), (ins GPR:$rj, uimm8:$seq), "$rj, $seq">;
// Other Miscellaneous Instructions
let hasSideEffects = 1, mayLoad = 0, mayStore = 0 in
-def ERTN : FmtI32<0b00000110010010000011100000000000>;
-def DBCL : MISC_I15<0b00000000001010101>;
-def IDLE : MISC_I15<0b00000110010010001>;
+def ERTN : FmtI32<0x06483800>;
+def DBCL : MISC_I15<0x002a8000>;
+def IDLE : MISC_I15<0x06488000>;
//===----------------------------------------------------------------------===//
// Privilege Intrinsics
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