[PATCH] D155587: [AMDGPU][RFC] Update isLegalAddressingMode for GFX9 SMEM signed offsets
Jay Foad via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 18 05:39:11 PDT 2023
foad created this revision.
Herald added subscribers: StephenFan, kerbowa, hiraditya, tpr, dstuttard, yaxunl, jvesely, kzhuravl, arsenm.
Herald added a project: All.
foad requested review of this revision.
Herald added subscribers: llvm-commits, wdng.
Herald added a project: LLVM.
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D155587
Files:
llvm/lib/Target/AMDGPU/SIISelLowering.cpp
Index: llvm/lib/Target/AMDGPU/SIISelLowering.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIISelLowering.cpp
+++ llvm/lib/Target/AMDGPU/SIISelLowering.cpp
@@ -1388,12 +1388,16 @@
// in 8-bits, it can use a smaller encoding.
if (!isUInt<32>(AM.BaseOffs / 4))
return false;
- } else if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) {
+ } else if (Subtarget->getGeneration() < AMDGPUSubtarget::GFX9) {
// On VI, these use the SMEM format and the offset is 20-bit in bytes.
if (!isUInt<20>(AM.BaseOffs))
return false;
- } else
- llvm_unreachable("unhandled generation");
+ } else {
+ // On GFX9 the offset is signed 21-bit in bytes (but must not be nagative
+ // S_BUFFER_* instructions).
+ if (!isInt<21>(AM.BaseOffs))
+ return false;
+ }
if (AM.Scale == 0) // r + i or just i, depending on HasBaseReg.
return true;
-------------- next part --------------
A non-text attachment was scrubbed...
Name: D155587.541478.patch
Type: text/x-patch
Size: 989 bytes
Desc: not available
URL: <http://lists.llvm.org/pipermail/llvm-commits/attachments/20230718/d3c6a3a1/attachment.bin>
More information about the llvm-commits
mailing list