[llvm] 4a81283 - AMDGPU: Generate and add fdiv tests
Matt Arsenault via llvm-commits
llvm-commits at lists.llvm.org
Tue Jul 18 03:49:06 PDT 2023
Author: Matt Arsenault
Date: 2023-07-18T06:38:05-04:00
New Revision: 4a81283b949b197b3f651e71aa3ef81095a4da93
URL: https://github.com/llvm/llvm-project/commit/4a81283b949b197b3f651e71aa3ef81095a4da93
DIFF: https://github.com/llvm/llvm-project/commit/4a81283b949b197b3f651e71aa3ef81095a4da93.diff
LOG: AMDGPU: Generate and add fdiv tests
Prepare for new lowering strategies because we somehow didn't have
enough of them already.
Added:
Modified:
llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
llvm/test/CodeGen/AMDGPU/fdiv.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
index 0948cda271b116..c40bb418f527c8 100644
--- a/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
+++ b/llvm/test/CodeGen/AMDGPU/GlobalISel/fdiv.f32.ll
@@ -1,6 +1,9 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE %s
-; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-FASTFMA %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=tahiti -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-FASTFMA %s
+
+; RUN: llc -global-isel -march=amdgcn -mcpu=pitcairn -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX6-IEEE,GFX6-IEEE-SLOWFMA %s
+; RUN: llc -global-isel -march=amdgcn -mcpu=pitcairn -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX6-FLUSH,GFX6-FLUSH-SLOWFMA %s
; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=ieee -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-IEEE,GFX89-IEEE %s
; RUN: llc -global-isel -march=amdgcn -mcpu=fiji -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GCN-FLUSH,GFX89-FLUSH %s
@@ -15,39 +18,73 @@
; RUN: llc -global-isel -march=amdgcn -mcpu=gfx1100 -denormal-fp-math=preserve-sign -verify-machineinstrs < %s | FileCheck -check-prefixes=GFX11,GFX11-FLUSH %s
define float @v_fdiv_f32(float %a, float %b) {
-; GFX6-IEEE-LABEL: v_fdiv_f32:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
-; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-FLUSH-LABEL: v_fdiv_f32:
-; GFX6-FLUSH: ; %bb.0:
-; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
-; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v1, v0
-; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_f32:
+; GFX6-FLUSH-FASTFMA: ; %bb.0:
+; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_f32:
+; GFX6-FLUSH-SLOWFMA: ; %bb.0:
+; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_f32:
; GFX89-IEEE: ; %bb.0:
@@ -191,21 +228,21 @@ define float @v_fdiv_f32_afn(float %a, float %b) {
}
define float @v_fdiv_f32_ulp25(float %a, float %b) {
-; GFX6-IEEE-LABEL: v_fdiv_f32_ulp25:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
-; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_ulp25:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_fdiv_f32_ulp25:
; GCN-FLUSH: ; %bb.0:
@@ -220,6 +257,22 @@ define float @v_fdiv_f32_ulp25(float %a, float %b) {
; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
+; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_ulp25:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
; GFX89-IEEE-LABEL: v_fdiv_f32_ulp25:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -302,39 +355,73 @@ define float @v_fdiv_f32_ulp25(float %a, float %b) {
}
define float @v_rcp_f32(float %x) {
-; GFX6-IEEE-LABEL: v_rcp_f32:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v1
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v2
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-FLUSH-LABEL: v_rcp_f32:
-; GFX6-FLUSH: ; %bb.0:
-; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
-; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
-; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v2
-; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
-; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v4
-; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
-; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
-; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_rcp_f32:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_f32:
+; GFX6-FLUSH-FASTFMA: ; %bb.0:
+; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_f32:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_f32:
+; GFX6-FLUSH-SLOWFMA: ; %bb.0:
+; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_rcp_f32:
; GFX89-IEEE: ; %bb.0:
@@ -452,39 +539,73 @@ define float @v_rcp_f32(float %x) {
}
define float @v_rcp_f32_arcp(float %x) {
-; GFX6-IEEE-LABEL: v_rcp_f32_arcp:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v2, v1
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v1, v2, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v2, v4, v2, v2
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v4, v3, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v1, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v1, -v1, v4, v3
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v1, v1, v2, v4
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-FLUSH-LABEL: v_rcp_f32_arcp:
-; GFX6-FLUSH: ; %bb.0:
-; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
-; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v2, v1
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v1, v2, 1.0
-; GFX6-FLUSH-NEXT: v_fma_f32 v2, v4, v2, v2
-; GFX6-FLUSH-NEXT: v_mul_f32_e32 v4, v3, v2
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v1, v4, v3
-; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v2, v4
-; GFX6-FLUSH-NEXT: v_fma_f32 v1, -v1, v4, v3
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT: v_div_fmas_f32 v1, v1, v2, v4
-; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
-; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_rcp_f32_arcp:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_f32_arcp:
+; GFX6-FLUSH-FASTFMA: ; %bb.0:
+; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_f32_arcp:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_f32_arcp:
+; GFX6-FLUSH-SLOWFMA: ; %bb.0:
+; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_rcp_f32_arcp:
; GFX89-IEEE: ; %bb.0:
@@ -710,21 +831,21 @@ define float @v_fdiv_f32_afn_ulp25(float %a, float %b) {
}
define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) {
-; GFX6-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
-; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v1, v0
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_f32_arcp_ulp25:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_fdiv_f32_arcp_ulp25:
; GCN-FLUSH: ; %bb.0:
@@ -739,6 +860,22 @@ define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) {
; GCN-FLUSH-NEXT: v_mul_f32_e32 v0, v2, v0
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
+; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_f32_arcp_ulp25:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
; GFX89-IEEE-LABEL: v_fdiv_f32_arcp_ulp25:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -821,63 +958,122 @@ define float @v_fdiv_f32_arcp_ulp25(float %a, float %b) {
}
define <2 x float> @v_fdiv_v2f32(<2 x float> %a, <2 x float> %b) {
-; GFX6-IEEE-LABEL: v_fdiv_v2f32:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4
-; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
-; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v5, v6, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v6, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-FLUSH-LABEL: v_fdiv_v2f32:
-; GFX6-FLUSH: ; %bb.0:
-; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
-; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v5, v4
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v4, v5, 1.0
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, v7, v5, v5
-; GFX6-FLUSH-NEXT: v_mul_f32_e32 v7, v6, v5
-; GFX6-FLUSH-NEXT: v_fma_f32 v8, -v4, v7, v6
-; GFX6-FLUSH-NEXT: v_fma_f32 v7, v8, v5, v7
-; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v4, v7, v6
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT: v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v6, v5
-; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v4, v2, v0
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT: v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-FLUSH-NEXT: v_fma_f32 v4, v4, v6, v6
-; GFX6-FLUSH-NEXT: v_mul_f32_e32 v6, v2, v4
-; GFX6-FLUSH-NEXT: v_fma_f32 v7, -v5, v6, v2
-; GFX6-FLUSH-NEXT: v_fma_f32 v6, v7, v4, v6
-; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v5, v6, v2
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v6
-; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v3, v1
-; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_v2f32:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v4, v5, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v7, v5, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v7, v6, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v8, -v4, v7, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, v8, v5, v7
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v4, v6, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v6, v2, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v5, v6, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v5, v6, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v1
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-FASTFMA-LABEL: v_fdiv_v2f32:
+; GFX6-FLUSH-FASTFMA: ; %bb.0:
+; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
+; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v5, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v7, -v4, v5, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v7, v5, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v7, v6, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v8, -v4, v7, v6
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v7, v8, v5, v7
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v4, v7, v6
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
+; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v4, v6, v6
+; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v6, v2, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v7, -v5, v6, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v5, v6, v2
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v1
+; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_v2f32:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v7, s[4:5], v1, v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v8, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v9, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v4, v8, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v8, v8
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v5, v9, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v9, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v10, v6, v8
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v11, v7, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v12, -v4, v10, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v13, -v5, v11, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, v12, v8, v10
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, v13, v9, v11
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v4, v10, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v5, v11, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v4, v4, v8, v10
+; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v5, v5, v9, v11
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v5, v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-SLOWFMA-LABEL: v_fdiv_v2f32:
+; GFX6-FLUSH-SLOWFMA: ; %bb.0:
+; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v2, v0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v6, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v7, -v4, v6, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, v7, v6, v6
+; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v7, v5, v6
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v8, -v4, v7, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v7, v8, v6, v7
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, -v4, v7, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v4, v4, v6, v7
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v6, vcc, v1, v3, v1
+; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v7, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v5, v7, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, v2, v7, v7
+; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v4, v6, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v7, -v5, v4, v6
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v7, v2, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v5, v4, v6
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v5, v2, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v1
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_fdiv_v2f32:
; GFX89-IEEE: ; %bb.0:
@@ -1109,32 +1305,32 @@ define <2 x float> @v_fdiv_v2f32_afn(<2 x float> %a, <2 x float> %b) {
}
define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
-; GFX6-IEEE-LABEL: v_fdiv_v2f32_ulp25:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4
-; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
-; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v5, v6, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v6, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_v2f32_ulp25:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v4, v5, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v7, v5, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v7, v6, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v8, -v4, v7, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, v8, v5, v7
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v4, v6, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v6, v2, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v5, v6, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v5, v6, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v1
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_fdiv_v2f32_ulp25:
; GCN-FLUSH: ; %bb.0:
@@ -1155,6 +1351,34 @@ define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v4, v1
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
+; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_v2f32_ulp25:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v7, s[4:5], v1, v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v8, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v9, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v4, v8, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v8, v8
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v5, v9, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v9, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v10, v6, v8
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v11, v7, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v12, -v4, v10, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v13, -v5, v11, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, v12, v8, v10
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, v13, v9, v11
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v4, v10, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v5, v11, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v4, v4, v8, v10
+; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v5, v5, v9, v11
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v5, v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
; GFX89-IEEE-LABEL: v_fdiv_v2f32_ulp25:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -1286,63 +1510,122 @@ define <2 x float> @v_fdiv_v2f32_ulp25(<2 x float> %a, <2 x float> %b) {
}
define <2 x float> @v_rcp_v2f32(<2 x float> %x) {
-; GFX6-IEEE-LABEL: v_rcp_v2f32:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
-; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-FLUSH-LABEL: v_rcp_v2f32:
-; GFX6-FLUSH: ; %bb.0:
-; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
-; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
-; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
-; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
-; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
-; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_rcp_v2f32:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_v2f32:
+; GFX6-FLUSH-FASTFMA: ; %bb.0:
+; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_v2f32:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v6, v2
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v7, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, -v2, v6, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, v8, v6, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, -v3, v7, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v7, v9, v7, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v8, v4, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v9, v5, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v2, v8, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v3, v9, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v6, v8
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v7, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v8, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v9, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v6, v8
+; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v7, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_v2f32:
+; GFX6-FLUSH-SLOWFMA: ; %bb.0:
+; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, v2, v5, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v2, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v5, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v3, v2, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_rcp_v2f32:
; GFX89-IEEE: ; %bb.0:
@@ -1543,63 +1826,122 @@ define <2 x float> @v_rcp_v2f32(<2 x float> %x) {
}
define <2 x float> @v_rcp_v2f32_arcp(<2 x float> %x) {
-; GFX6-IEEE-LABEL: v_rcp_v2f32_arcp:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v3, v2
-; GFX6-IEEE-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-IEEE-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v4, v3
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v5
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
-;
-; GFX6-FLUSH-LABEL: v_rcp_v2f32_arcp:
-; GFX6-FLUSH: ; %bb.0:
-; GFX6-FLUSH-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
-; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v3, v2
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v2, v3, 1.0
-; GFX6-FLUSH-NEXT: v_fma_f32 v3, v5, v3, v3
-; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v4, v3
-; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v2, v5, v4
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v3, v5
-; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v2, v5, v4
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v3, v5
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
-; GFX6-FLUSH-NEXT: v_rcp_f32_e32 v4, v3
-; GFX6-FLUSH-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
-; GFX6-FLUSH-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, -v3, v4, 1.0
-; GFX6-FLUSH-NEXT: v_fma_f32 v4, v5, v4, v4
-; GFX6-FLUSH-NEXT: v_mul_f32_e32 v5, v2, v4
-; GFX6-FLUSH-NEXT: v_fma_f32 v6, -v3, v5, v2
-; GFX6-FLUSH-NEXT: v_fma_f32 v5, v6, v4, v5
-; GFX6-FLUSH-NEXT: v_fma_f32 v2, -v3, v5, v2
-; GFX6-FLUSH-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX6-FLUSH-NEXT: v_div_fmas_f32 v2, v2, v4, v5
-; GFX6-FLUSH-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
-; GFX6-FLUSH-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_rcp_v2f32_arcp:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-FASTFMA-LABEL: v_rcp_v2f32_arcp:
+; GFX6-FLUSH-FASTFMA: ; %bb.0:
+; GFX6-FLUSH-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, v1, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v2
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
+; GFX6-FLUSH-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-FLUSH-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
+; GFX6-FLUSH-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-IEEE-SLOWFMA-LABEL: v_rcp_v2f32_arcp:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], 1.0, v1, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v6, v2
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v7, v3
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, -v2, v6, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v6, v8, v6, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, -v3, v7, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v7, v9, v7, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v8, v4, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v9, v5, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v2, v8, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v3, v9, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v6, v8
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v7, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v8, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v9, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v6, v8
+; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v7, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v3, v1, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-FLUSH-SLOWFMA-LABEL: v_rcp_v2f32_arcp:
+; GFX6-FLUSH-SLOWFMA: ; %bb.0:
+; GFX6-FLUSH-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v0, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, 1.0, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, 1.0, v1, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v0, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v2, v2, v5, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_mul_f32_e32 v5, v4, v2
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v5, v6, v2, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v5, v4
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fmas_f32 v2, v3, v2, v5
+; GFX6-FLUSH-SLOWFMA-NEXT: v_div_fixup_f32 v1, v2, v1, 1.0
+; GFX6-FLUSH-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
;
; GFX89-IEEE-LABEL: v_rcp_v2f32_arcp:
; GFX89-IEEE: ; %bb.0:
@@ -1935,32 +2277,32 @@ define <2 x float> @v_fdiv_v2f32_afn_ulp25(<2 x float> %a, <2 x float> %b) {
}
define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {
-; GFX6-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
-; GFX6-IEEE: ; %bb.0:
-; GFX6-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
-; GFX6-IEEE-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v5, v4
-; GFX6-IEEE-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v4, v5, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v5, v7, v5, v5
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v7, v6, v5
-; GFX6-IEEE-NEXT: v_fma_f32 v8, -v4, v7, v6
-; GFX6-IEEE-NEXT: v_fma_f32 v7, v8, v5, v7
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v4, v7, v6
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v4, v4, v5, v7
-; GFX6-IEEE-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
-; GFX6-IEEE-NEXT: v_rcp_f32_e32 v6, v5
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v0, v4, v2, v0
-; GFX6-IEEE-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
-; GFX6-IEEE-NEXT: v_fma_f32 v4, -v5, v6, 1.0
-; GFX6-IEEE-NEXT: v_fma_f32 v4, v4, v6, v6
-; GFX6-IEEE-NEXT: v_mul_f32_e32 v6, v2, v4
-; GFX6-IEEE-NEXT: v_fma_f32 v7, -v5, v6, v2
-; GFX6-IEEE-NEXT: v_fma_f32 v6, v7, v4, v6
-; GFX6-IEEE-NEXT: v_fma_f32 v2, -v5, v6, v2
-; GFX6-IEEE-NEXT: v_div_fmas_f32 v2, v2, v4, v6
-; GFX6-IEEE-NEXT: v_div_fixup_f32 v1, v2, v3, v1
-; GFX6-IEEE-NEXT: s_setpc_b64 s[30:31]
+; GFX6-IEEE-FASTFMA-LABEL: v_fdiv_v2f32_arcp_ulp25:
+; GFX6-IEEE-FASTFMA: ; %bb.0:
+; GFX6-IEEE-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v5, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v4, v5, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v5, v7, v5, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v7, v6, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v8, -v4, v7, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, v8, v5, v7
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v4, v7, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v4, v4, v5, v7
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
+; GFX6-IEEE-FASTFMA-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
+; GFX6-IEEE-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, v1, v3, v1
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, -v5, v6, 1.0
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v4, v4, v6, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_mul_f32_e32 v6, v2, v4
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v7, -v5, v6, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_fma_f32 v2, -v5, v6, v2
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v6
+; GFX6-IEEE-FASTFMA-NEXT: v_div_fixup_f32 v1, v2, v3, v1
+; GFX6-IEEE-FASTFMA-NEXT: s_setpc_b64 s[30:31]
;
; GCN-FLUSH-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GCN-FLUSH: ; %bb.0:
@@ -1981,6 +2323,34 @@ define <2 x float> @v_fdiv_v2f32_arcp_ulp25(<2 x float> %a, <2 x float> %b) {
; GCN-FLUSH-NEXT: v_mul_f32_e32 v1, v4, v1
; GCN-FLUSH-NEXT: s_setpc_b64 s[30:31]
;
+; GFX6-IEEE-SLOWFMA-LABEL: v_fdiv_v2f32_arcp_ulp25:
+; GFX6-IEEE-SLOWFMA: ; %bb.0:
+; GFX6-IEEE-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v4, s[4:5], v2, v2, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v5, s[4:5], v3, v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v6, vcc, v0, v2, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_scale_f32 v7, s[4:5], v1, v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v8, v4
+; GFX6-IEEE-SLOWFMA-NEXT: v_rcp_f32_e32 v9, v5
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, -v4, v8, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v8, v10, v8, v8
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, -v5, v9, 1.0
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v9, v11, v9, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v10, v6, v8
+; GFX6-IEEE-SLOWFMA-NEXT: v_mul_f32_e32 v11, v7, v9
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v12, -v4, v10, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v13, -v5, v11, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v10, v12, v8, v10
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v11, v13, v9, v11
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v4, -v4, v10, v6
+; GFX6-IEEE-SLOWFMA-NEXT: v_fma_f32 v5, -v5, v11, v7
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v4, v4, v8, v10
+; GFX6-IEEE-SLOWFMA-NEXT: s_mov_b64 vcc, s[4:5]
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fmas_f32 v5, v5, v9, v11
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v0, v4, v2, v0
+; GFX6-IEEE-SLOWFMA-NEXT: v_div_fixup_f32 v1, v5, v3, v1
+; GFX6-IEEE-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
; GFX89-IEEE-LABEL: v_fdiv_v2f32_arcp_ulp25:
; GFX89-IEEE: ; %bb.0:
; GFX89-IEEE-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
@@ -2143,3 +2513,6 @@ define <2 x float> @v_fdiv_v2f32_arcp_afn_ulp25(<2 x float> %a, <2 x float> %b)
}
!0 = !{float 2.500000e+00}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX6-FLUSH: {{.*}}
+; GFX6-IEEE: {{.*}}
diff --git a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
index 47b76d8981610c..216ee19fcb85ba 100644
--- a/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-fdiv.ll
@@ -1949,6 +1949,158 @@ define <4 x float> @fdiv_constant_f32_vector(ptr addrspace(1) %out, <2 x float>
ret <4 x float> %const.partial.rcp
}
+define amdgpu_kernel void @fdiv_fpmath_f32_nosub_lhs(ptr addrspace(1) %out, float nofpclass(sub) %a, float %b) {
+; IEEE-LABEL: define amdgpu_kernel void @fdiv_fpmath_f32_nosub_lhs
+; IEEE-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(sub) [[A:%.*]], float [[B:%.*]]) #[[ATTR1]] {
+; IEEE-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]]
+; IEEE-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1
+; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[MD_1ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !2
+; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[MD_25ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !0
+; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[MD_3ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !3
+; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[B]])
+; IEEE-NEXT: [[FAST_MD_25ULP:%.*]] = fmul fast float [[A]], [[TMP1]]
+; IEEE-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[TMP2:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[B]])
+; IEEE-NEXT: [[AFN_MD_25ULP:%.*]] = fmul afn float [[A]], [[TMP2]]
+; IEEE-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]]
+; IEEE-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[ARCP_MD_25ULP:%.*]] = fdiv arcp float [[A]], [[B]], !fpmath !0
+; IEEE-NEXT: store volatile float [[ARCP_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[ARCP_MD_1ULP:%.*]] = fdiv arcp float [[A]], [[B]], !fpmath !2
+; IEEE-NEXT: store volatile float [[ARCP_MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: ret void
+;
+; DAZ-LABEL: define amdgpu_kernel void @fdiv_fpmath_f32_nosub_lhs
+; DAZ-SAME: (ptr addrspace(1) [[OUT:%.*]], float nofpclass(sub) [[A:%.*]], float [[B:%.*]]) #[[ATTR1]] {
+; DAZ-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]]
+; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1
+; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[MD_1ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !2
+; DAZ-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.fdiv.fast(float [[A]], float [[B]])
+; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.fdiv.fast(float [[A]], float [[B]])
+; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[B]])
+; DAZ-NEXT: [[FAST_MD_25ULP:%.*]] = fmul fast float [[A]], [[TMP1]]
+; DAZ-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[TMP2:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[B]])
+; DAZ-NEXT: [[AFN_MD_25ULP:%.*]] = fmul afn float [[A]], [[TMP2]]
+; DAZ-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]]
+; DAZ-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[ARCP_MD_25ULP:%.*]] = call arcp float @llvm.amdgcn.fdiv.fast(float [[A]], float [[B]])
+; DAZ-NEXT: store volatile float [[ARCP_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[ARCP_MD_1ULP:%.*]] = fdiv arcp float [[A]], [[B]], !fpmath !2
+; DAZ-NEXT: store volatile float [[ARCP_MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: ret void
+;
+ %no.md = fdiv float %a, %b
+ store volatile float %no.md, ptr addrspace(1) %out, align 4
+ %md.half.ulp = fdiv float %a, %b, !fpmath !1
+ store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
+ %md.1ulp = fdiv float %a, %b, !fpmath !2
+ store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
+ %md.25ulp = fdiv float %a, %b, !fpmath !0
+ store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
+ %md.3ulp = fdiv float %a, %b, !fpmath !3
+ store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
+ %fast.md.25ulp = fdiv fast float %a, %b, !fpmath !0
+ store volatile float %fast.md.25ulp, ptr addrspace(1) %out, align 4
+ %afn.md.25ulp = fdiv afn float %a, %b, !fpmath !0
+ store volatile float %afn.md.25ulp, ptr addrspace(1) %out, align 4
+ %no.md.arcp = fdiv arcp float %a, %b
+ store volatile float %no.md.arcp, ptr addrspace(1) %out, align 4
+ %arcp.md.25ulp = fdiv arcp float %a, %b, !fpmath !0
+ store volatile float %arcp.md.25ulp, ptr addrspace(1) %out, align 4
+ %arcp.md.1ulp = fdiv arcp float %a, %b, !fpmath !2
+ store volatile float %arcp.md.1ulp, ptr addrspace(1) %out, align 4
+ ret void
+}
+
+define amdgpu_kernel void @fdiv_fpmath_f32_nosub_rhs(ptr addrspace(1) %out, float %a, float nofpclass(sub) %b) {
+; IEEE-LABEL: define amdgpu_kernel void @fdiv_fpmath_f32_nosub_rhs
+; IEEE-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float nofpclass(sub) [[B:%.*]]) #[[ATTR1]] {
+; IEEE-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]]
+; IEEE-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1
+; IEEE-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[MD_1ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !2
+; IEEE-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[MD_25ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !0
+; IEEE-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[MD_3ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !3
+; IEEE-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[B]])
+; IEEE-NEXT: [[FAST_MD_25ULP:%.*]] = fmul fast float [[A]], [[TMP1]]
+; IEEE-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[TMP2:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[B]])
+; IEEE-NEXT: [[AFN_MD_25ULP:%.*]] = fmul afn float [[A]], [[TMP2]]
+; IEEE-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]]
+; IEEE-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[ARCP_MD_25ULP:%.*]] = fdiv arcp float [[A]], [[B]], !fpmath !0
+; IEEE-NEXT: store volatile float [[ARCP_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: [[ARCP_MD_1ULP:%.*]] = fdiv arcp float [[A]], [[B]], !fpmath !2
+; IEEE-NEXT: store volatile float [[ARCP_MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
+; IEEE-NEXT: ret void
+;
+; DAZ-LABEL: define amdgpu_kernel void @fdiv_fpmath_f32_nosub_rhs
+; DAZ-SAME: (ptr addrspace(1) [[OUT:%.*]], float [[A:%.*]], float nofpclass(sub) [[B:%.*]]) #[[ATTR1]] {
+; DAZ-NEXT: [[NO_MD:%.*]] = fdiv float [[A]], [[B]]
+; DAZ-NEXT: store volatile float [[NO_MD]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[MD_HALF_ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !1
+; DAZ-NEXT: store volatile float [[MD_HALF_ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[MD_1ULP:%.*]] = fdiv float [[A]], [[B]], !fpmath !2
+; DAZ-NEXT: store volatile float [[MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[MD_25ULP:%.*]] = call float @llvm.amdgcn.fdiv.fast(float [[A]], float [[B]])
+; DAZ-NEXT: store volatile float [[MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[MD_3ULP:%.*]] = call float @llvm.amdgcn.fdiv.fast(float [[A]], float [[B]])
+; DAZ-NEXT: store volatile float [[MD_3ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[TMP1:%.*]] = call fast float @llvm.amdgcn.rcp.f32(float [[B]])
+; DAZ-NEXT: [[FAST_MD_25ULP:%.*]] = fmul fast float [[A]], [[TMP1]]
+; DAZ-NEXT: store volatile float [[FAST_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[TMP2:%.*]] = call afn float @llvm.amdgcn.rcp.f32(float [[B]])
+; DAZ-NEXT: [[AFN_MD_25ULP:%.*]] = fmul afn float [[A]], [[TMP2]]
+; DAZ-NEXT: store volatile float [[AFN_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[NO_MD_ARCP:%.*]] = fdiv arcp float [[A]], [[B]]
+; DAZ-NEXT: store volatile float [[NO_MD_ARCP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[ARCP_MD_25ULP:%.*]] = call arcp float @llvm.amdgcn.fdiv.fast(float [[A]], float [[B]])
+; DAZ-NEXT: store volatile float [[ARCP_MD_25ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: [[ARCP_MD_1ULP:%.*]] = fdiv arcp float [[A]], [[B]], !fpmath !2
+; DAZ-NEXT: store volatile float [[ARCP_MD_1ULP]], ptr addrspace(1) [[OUT]], align 4
+; DAZ-NEXT: ret void
+;
+ %no.md = fdiv float %a, %b
+ store volatile float %no.md, ptr addrspace(1) %out, align 4
+ %md.half.ulp = fdiv float %a, %b, !fpmath !1
+ store volatile float %md.half.ulp, ptr addrspace(1) %out, align 4
+ %md.1ulp = fdiv float %a, %b, !fpmath !2
+ store volatile float %md.1ulp, ptr addrspace(1) %out, align 4
+ %md.25ulp = fdiv float %a, %b, !fpmath !0
+ store volatile float %md.25ulp, ptr addrspace(1) %out, align 4
+ %md.3ulp = fdiv float %a, %b, !fpmath !3
+ store volatile float %md.3ulp, ptr addrspace(1) %out, align 4
+ %fast.md.25ulp = fdiv fast float %a, %b, !fpmath !0
+ store volatile float %fast.md.25ulp, ptr addrspace(1) %out, align 4
+ %afn.md.25ulp = fdiv afn float %a, %b, !fpmath !0
+ store volatile float %afn.md.25ulp, ptr addrspace(1) %out, align 4
+ %no.md.arcp = fdiv arcp float %a, %b
+ store volatile float %no.md.arcp, ptr addrspace(1) %out, align 4
+ %arcp.md.25ulp = fdiv arcp float %a, %b, !fpmath !0
+ store volatile float %arcp.md.25ulp, ptr addrspace(1) %out, align 4
+ %arcp.md.1ulp = fdiv arcp float %a, %b, !fpmath !2
+ store volatile float %arcp.md.1ulp, ptr addrspace(1) %out, align 4
+ ret void
+}
+
declare float @llvm.sqrt.f32(float)
declare float @llvm.fabs.f32(float)
declare <2 x float> @llvm.sqrt.v2f32(<2 x float>)
diff --git a/llvm/test/CodeGen/AMDGPU/fdiv.ll b/llvm/test/CodeGen/AMDGPU/fdiv.ll
index 5a6506f31582b2..0a126fcc216957 100644
--- a/llvm/test/CodeGen/AMDGPU/fdiv.ll
+++ b/llvm/test/CodeGen/AMDGPU/fdiv.ll
@@ -1,9 +1,11 @@
-; RUN: llc -march=amdgcn -mcpu=tahiti -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,PREGFX10,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,PREGFX10,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=fiji -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,PREGFX10,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,FUNC %s
-; RUN: llc -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck -check-prefixes=GCN,GFX10,FUNC %s
-; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=R600 -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
+; RUN: llc -march=amdgcn -mcpu=tahiti < %s | FileCheck -check-prefixes=GCN,GFX678,GFX67,GFX6,GFX6-FASTFMA %s
+; RUN: llc -march=amdgcn -mcpu=pitcairn < %s | FileCheck -check-prefixes=GCN,GFX678,GFX67,GFX6,GFX6-SLOWFMA %s
+; RUN: llc -march=amdgcn -mcpu=hawaii < %s | FileCheck -check-prefixes=GCN,GFX678,GFX67,GFX7 %s
+; RUN: llc -march=amdgcn -mcpu=fiji < %s | FileCheck -check-prefixes=GCN,GFX678,GFX8 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GCN,GFX10 %s
+; RUN: llc -march=amdgcn -mcpu=gfx1100 -amdgpu-enable-delay-alu=0 < %s | FileCheck -check-prefixes=GCN,GFX11 %s
+; RUN: llc -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
; These tests check that fdiv is expanded correctly and also test that the
; scheduler is scheduling the RECIP_IEEE and MUL_IEEE instructions in separate
@@ -11,78 +13,400 @@
; These test check that fdiv using unsafe_fp_math, coarse fp div, and IEEE754 fp div.
-; FUNC-LABEL: {{^}}fdiv_f32:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
-
-; GCN: v_div_scale_f32 [[NUM_SCALE:v[0-9]+]]
-; GCN-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
-; GCN-DAG: v_rcp_f32_e32 [[NUM_RCP:v[0-9]+]], [[NUM_SCALE]]
-
-; PREGFX10: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX10: s_denorm_mode 15
-; GCN: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
-; PREGFX10: v_fma_f32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]], [[NUM_RCP]]
-; GFX10: v_fmac_f32_e32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]]
-; GCN: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
-; GCN: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
-; PREGFX10: v_fma_f32 [[E:v[0-9]+]], [[D]], [[B]], [[C]]
-; GFX10: v_fmac_f32_e32 [[E:v[0-9]+]], [[D]], [[B]]
-; GCN: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
-; PREGFX10: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX10: s_denorm_mode 12
-; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
-; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
-define amdgpu_kernel void @fdiv_f32(ptr addrspace(1) %out, float %a, float %b) #0 {
+define amdgpu_kernel void @s_fdiv_f32_ninf(ptr addrspace(1) %out, float %a, float %b) #0 {
+; GFX6-FASTFMA-LABEL: s_fdiv_f32_ninf:
+; GFX6-FASTFMA: ; %bb.0: ; %entry
+; GFX6-FASTFMA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-FASTFMA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, -1
+; GFX6-FASTFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-FASTFMA-NEXT: s_mov_b32 s4, s0
+; GFX6-FASTFMA-NEXT: s_mov_b32 s5, s1
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[0:1], s3, s3, v1
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v0, s3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v0, vcc, s2, v0, s2
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v0, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v4, v0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v0, -v2, v4, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v0, v0, v3, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v0, s3, v1
+; GFX6-FASTFMA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-FASTFMA-NEXT: s_endpgm
+;
+; GFX6-SLOWFMA-LABEL: s_fdiv_f32_ninf:
+; GFX6-SLOWFMA: ; %bb.0: ; %entry
+; GFX6-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, -1
+; GFX6-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v2, s3
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s4, s0
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s5, s1
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s3, v0
+; GFX6-SLOWFMA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-SLOWFMA-NEXT: s_endpgm
+;
+; GFX7-LABEL: s_fdiv_f32_ninf:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX7-NEXT: s_mov_b32 s7, 0xf000
+; GFX7-NEXT: s_mov_b32 s6, -1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v1, s2
+; GFX7-NEXT: s_mov_b32 s4, s0
+; GFX7-NEXT: s_mov_b32 s5, s1
+; GFX7-NEXT: v_div_scale_f32 v2, s[0:1], s3, s3, v1
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_mov_b32_e32 v0, s3
+; GFX7-NEXT: v_div_scale_f32 v0, vcc, s2, v0, s2
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v4, v0, v3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v4, v0
+; GFX7-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX7-NEXT: v_fma_f32 v0, -v2, v4, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v0, v0, v3, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v0, s3, v1
+; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_f32_ninf:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v2, v1, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_f32_ninf:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v0, s4, s3, s3, s2
+; GFX10-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v0
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX10-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX10-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX10-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_div_fixup_f32 v0, v0, s3, s2
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_f32_ninf:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v0, null, s3, s3, s2
+; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v0
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX11-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX11-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_div_fixup_f32 v0, v0, s3, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_f32_ninf:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].W,
+; EG-NEXT: MUL_IEEE T0.X, KC0[2].Z, PS,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv ninf float %a, %b
store float %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_f32_denormals:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].Z, PS
-
-; GCN: v_div_scale_f32 [[NUM_SCALE:v[0-9]+]]
-; GCN-DAG: v_rcp_f32_e32 [[NUM_RCP:v[0-9]+]], [[NUM_SCALE]]
-
-; PREGFX10-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
-; PREGFX10-NOT: s_setreg
-; PREGFX10: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
-; PREGFX10: v_fma_f32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]], [[NUM_RCP]]
-; PREGFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
-; PREGFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
-; PREGFX10: v_fma_f32 [[E:v[0-9]+]], [[D]], [[B]], [[C]]
-; PREGFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
-; PREGFX10-NOT: s_setreg
-
-; GFX10-NOT: s_denorm_mode
-; GFX10: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
-; GFX10: v_fmac_f32_e32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]]
-; GFX10: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
-; GFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
-; GFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
-; GFX10: v_fmac_f32_e32 [[E:v[0-9]+]], [[D]], [[B]]
-; GFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
-; GFX10-NOT: s_denorm_mode
-
-; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
-; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
-define amdgpu_kernel void @fdiv_f32_denormals(ptr addrspace(1) %out, float %a, float %b) #2 {
+define amdgpu_kernel void @s_fdiv_f32_ieee(ptr addrspace(1) %out, float %a, float %b) #1 {
+; GFX6-FASTFMA-LABEL: s_fdiv_f32_ieee:
+; GFX6-FASTFMA: ; %bb.0: ; %entry
+; GFX6-FASTFMA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-FASTFMA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, -1
+; GFX6-FASTFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s2, v3, s2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: s_mov_b32 s4, s0
+; GFX6-FASTFMA-NEXT: s_mov_b32 s5, s1
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s3, v0
+; GFX6-FASTFMA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-FASTFMA-NEXT: s_endpgm
+;
+; GFX6-SLOWFMA-LABEL: s_fdiv_f32_ieee:
+; GFX6-SLOWFMA: ; %bb.0: ; %entry
+; GFX6-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, -1
+; GFX6-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v2, s3
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s4, s0
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s5, s1
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s3, v0
+; GFX6-SLOWFMA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-SLOWFMA-NEXT: s_endpgm
+;
+; GFX7-LABEL: s_fdiv_f32_ieee:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX7-NEXT: s_mov_b32 s7, 0xf000
+; GFX7-NEXT: s_mov_b32 s6, -1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, s2, v3, s2
+; GFX7-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: s_mov_b32 s4, s0
+; GFX7-NEXT: s_mov_b32 s5, s1
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, s3, v0
+; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_f32_ieee:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v2, v1, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_f32_ieee:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v0, s4, s3, s3, s2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v0
+; GFX10-NEXT: v_fma_f32 v2, -v0, v1, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v1, v2, v1
+; GFX10-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
+; GFX10-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX10-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX10-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX10-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_div_fixup_f32 v0, v0, s3, s2
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_f32_ieee:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v0, null, s3, s3, s2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v0
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v2, -v0, v1, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v1
+; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
+; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX11-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX11-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX11-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_div_fixup_f32 v0, v0, s3, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_f32_ieee:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].W,
+; EG-NEXT: MUL_IEEE T0.X, KC0[2].Z, PS,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv float %a, %b
store float %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_25ulp_f32:
-; GCN: v_cndmask_b32
-; GCN: v_mul_f32
-; GCN: v_rcp_f32
-; GCN: v_mul_f32
-; GCN: v_mul_f32
-define amdgpu_kernel void @fdiv_25ulp_f32(ptr addrspace(1) %out, float %a, float %b) #0 {
+define amdgpu_kernel void @s_fdiv_25ulp_f32(ptr addrspace(1) %out, float %a, float %b) #0 {
+; GFX67-LABEL: s_fdiv_25ulp_f32:
+; GFX67: ; %bb.0: ; %entry
+; GFX67-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX67-NEXT: v_mov_b32_e32 v0, 0x6f800000
+; GFX67-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX67-NEXT: s_mov_b32 s7, 0xf000
+; GFX67-NEXT: s_mov_b32 s6, -1
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_cmp_gt_f32_e64 vcc, |s3|, v0
+; GFX67-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX67-NEXT: v_mul_f32_e32 v1, s3, v0
+; GFX67-NEXT: v_rcp_f32_e32 v1, v1
+; GFX67-NEXT: s_mov_b32 s4, s0
+; GFX67-NEXT: s_mov_b32 s5, s1
+; GFX67-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX67-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX67-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_25ulp_f32:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x6f800000
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_cmp_gt_f32_e64 vcc, |s3|, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v0, 1.0, v1, vcc
+; GFX8-NEXT: v_mul_f32_e32 v1, s3, v0
+; GFX8-NEXT: v_rcp_f32_e32 v1, v1
+; GFX8-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX8-NEXT: v_mul_f32_e32 v2, v0, v1
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_25ulp_f32:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |s3|
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e32 v1, s3, v0
+; GFX10-NEXT: v_rcp_f32_e32 v1, v1
+; GFX10-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT: global_store_dword v2, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_25ulp_f32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |s3|
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x2f800000, s4
+; GFX11-NEXT: v_mul_f32_e32 v1, s3, v0
+; GFX11-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v1, s2, v1
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: global_store_b32 v2, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_25ulp_f32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].W,
+; EG-NEXT: MUL_IEEE T0.X, KC0[2].Z, PS,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv float %a, %b, !fpmath !0
store float %fdiv, ptr addrspace(1) %out
@@ -90,169 +414,1531 @@ entry:
}
; Use correct fdiv
-; FUNC-LABEL: {{^}}fdiv_25ulp_denormals_f32:
-; GCN: v_fma_f32
-; GCN: v_div_fmas_f32
-; GCN: v_div_fixup_f32
-define amdgpu_kernel void @fdiv_25ulp_denormals_f32(ptr addrspace(1) %out, float %a, float %b) #2 {
+define amdgpu_kernel void @s_fdiv_25ulp_ieee_f32(ptr addrspace(1) %out, float %a, float %b) #1 {
+; GFX6-FASTFMA-LABEL: s_fdiv_25ulp_ieee_f32:
+; GFX6-FASTFMA: ; %bb.0: ; %entry
+; GFX6-FASTFMA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-FASTFMA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, -1
+; GFX6-FASTFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v3, s3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s2, v3, s2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: s_mov_b32 s4, s0
+; GFX6-FASTFMA-NEXT: s_mov_b32 s5, s1
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s3, v0
+; GFX6-FASTFMA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-FASTFMA-NEXT: s_endpgm
+;
+; GFX6-SLOWFMA-LABEL: s_fdiv_25ulp_ieee_f32:
+; GFX6-SLOWFMA: ; %bb.0: ; %entry
+; GFX6-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, -1
+; GFX6-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v2, s3
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s4, s0
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s5, s1
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s3, v0
+; GFX6-SLOWFMA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-SLOWFMA-NEXT: s_endpgm
+;
+; GFX7-LABEL: s_fdiv_25ulp_ieee_f32:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX7-NEXT: s_mov_b32 s7, 0xf000
+; GFX7-NEXT: s_mov_b32 s6, -1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v0, s2
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_mov_b32_e32 v3, s3
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, s2, v3, s2
+; GFX7-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: s_mov_b32 s4, s0
+; GFX7-NEXT: s_mov_b32 s5, s1
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, s3, v0
+; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_25ulp_ieee_f32:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v2, v1, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_25ulp_ieee_f32:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v0, s4, s3, s3, s2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v0
+; GFX10-NEXT: v_fma_f32 v2, -v0, v1, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v1, v2, v1
+; GFX10-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
+; GFX10-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX10-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX10-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX10-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_div_fixup_f32 v0, v0, s3, s2
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_25ulp_ieee_f32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v0, null, s3, s3, s2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v0
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v2, -v0, v1, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v1
+; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
+; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX11-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX11-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX11-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_div_fixup_f32 v0, v0, s3, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_25ulp_ieee_f32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].W,
+; EG-NEXT: MUL_IEEE T0.X, KC0[2].Z, PS,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv float %a, %b, !fpmath !0
store float %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_fast_denormals_f32:
-; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
-; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
-; GCN-NOT: [[RESULT]]
-; PREGFX10-NOT: s_setreg
-; GFX10-NOT: s_denorm_mode
-; GCN: buffer_store_{{dword|b32}} [[RESULT]]
-define amdgpu_kernel void @fdiv_fast_denormals_f32(ptr addrspace(1) %out, float %a, float %b) #2 {
+define amdgpu_kernel void @s_fdiv_fast_ieee_f32(ptr addrspace(1) %out, float %a, float %b) #1 {
+; GFX67-LABEL: s_fdiv_fast_ieee_f32:
+; GFX67: ; %bb.0: ; %entry
+; GFX67-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX67-NEXT: s_mov_b32 s7, 0xf000
+; GFX67-NEXT: s_mov_b32 s6, -1
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_rcp_f32_e32 v0, s3
+; GFX67-NEXT: s_mov_b32 s4, s0
+; GFX67-NEXT: s_mov_b32 s5, s1
+; GFX67-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX67-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_fast_ieee_f32:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_rcp_f32_e32 v0, s3
+; GFX8-NEXT: v_mul_f32_e32 v2, s2, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_fast_ieee_f32:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f32_e32 v0, s3
+; GFX10-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_fast_ieee_f32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f32_e32 v0, s3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, s2, v0
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_fast_ieee_f32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].W,
+; EG-NEXT: MUL_IEEE T0.X, PS, KC0[2].Z,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv fast float %a, %b
store float %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_f32_fast_math:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[2].Z,
-
-; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
-; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
-; GCN-NOT: [[RESULT]]
-; GCN: buffer_store_{{dword|b32}} [[RESULT]]
-define amdgpu_kernel void @fdiv_f32_fast_math(ptr addrspace(1) %out, float %a, float %b) #0 {
+define amdgpu_kernel void @s_fdiv_f32_fast_math(ptr addrspace(1) %out, float %a, float %b) #0 {
+; GFX67-LABEL: s_fdiv_f32_fast_math:
+; GFX67: ; %bb.0: ; %entry
+; GFX67-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX67-NEXT: s_mov_b32 s7, 0xf000
+; GFX67-NEXT: s_mov_b32 s6, -1
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_rcp_f32_e32 v0, s3
+; GFX67-NEXT: s_mov_b32 s4, s0
+; GFX67-NEXT: s_mov_b32 s5, s1
+; GFX67-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX67-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_f32_fast_math:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_rcp_f32_e32 v0, s3
+; GFX8-NEXT: v_mul_f32_e32 v2, s2, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_f32_fast_math:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f32_e32 v0, s3
+; GFX10-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_f32_fast_math:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f32_e32 v0, s3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, s2, v0
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_f32_fast_math:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].W,
+; EG-NEXT: MUL_IEEE T0.X, PS, KC0[2].Z,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv fast float %a, %b
store float %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_ulp25_f32_fast_math:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[2].Z,
-
-; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
-; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
-; GCN-NOT: [[RESULT]]
-; GCN: buffer_store_{{dword|b32}} [[RESULT]]
-define amdgpu_kernel void @fdiv_ulp25_f32_fast_math(ptr addrspace(1) %out, float %a, float %b) #0 {
+define amdgpu_kernel void @s_fdiv_ulp25_f32_fast_math(ptr addrspace(1) %out, float %a, float %b) #0 {
+; GFX67-LABEL: s_fdiv_ulp25_f32_fast_math:
+; GFX67: ; %bb.0: ; %entry
+; GFX67-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX67-NEXT: s_mov_b32 s7, 0xf000
+; GFX67-NEXT: s_mov_b32 s6, -1
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_rcp_f32_e32 v0, s3
+; GFX67-NEXT: s_mov_b32 s4, s0
+; GFX67-NEXT: s_mov_b32 s5, s1
+; GFX67-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX67-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_ulp25_f32_fast_math:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_rcp_f32_e32 v0, s3
+; GFX8-NEXT: v_mul_f32_e32 v2, s2, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_ulp25_f32_fast_math:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f32_e32 v0, s3
+; GFX10-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_ulp25_f32_fast_math:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f32_e32 v0, s3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, s2, v0
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_ulp25_f32_fast_math:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].W,
+; EG-NEXT: MUL_IEEE T0.X, PS, KC0[2].Z,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv fast float %a, %b, !fpmath !0
store float %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_f32_arcp_daz:
-; GCN: v_div_scale_f32
-; GCN-DAG: v_rcp_f32
-; GCN-DAG: v_div_scale_f32
-; GCN: {{s_setreg_imm32_b32|s_denorm_mode}}
-; GCN: v_fma{{c?}}_f32
-; GCN: v_fma{{c?}}_f32
-; GCN: v_fma{{c?}}_f32
-; GCN: v_fma{{c?}}_f32
-; GCN: {{s_setreg_imm32_b32|s_denorm_mode}}
-; GCN: v_div_fmas_f32
-; GCN: v_div_fixup_f32
-; GCN-NOT: v_mul_f32
-define amdgpu_kernel void @fdiv_f32_arcp_daz(ptr addrspace(1) %out, float %a, float %b) #0 {
+define amdgpu_kernel void @s_fdiv_f32_arcp_daz(ptr addrspace(1) %out, float %a, float %b) #0 {
+; GFX6-FASTFMA-LABEL: s_fdiv_f32_arcp_daz:
+; GFX6-FASTFMA: ; %bb.0: ; %entry
+; GFX6-FASTFMA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-FASTFMA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, -1
+; GFX6-FASTFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v1, s2
+; GFX6-FASTFMA-NEXT: s_mov_b32 s4, s0
+; GFX6-FASTFMA-NEXT: s_mov_b32 s5, s1
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[0:1], s3, s3, v1
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v0, s3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v0, vcc, s2, v0, s2
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v0, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v4, v0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v0, -v2, v4, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v0, v0, v3, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v0, s3, v1
+; GFX6-FASTFMA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-FASTFMA-NEXT: s_endpgm
+;
+; GFX6-SLOWFMA-LABEL: s_fdiv_f32_arcp_daz:
+; GFX6-SLOWFMA: ; %bb.0: ; %entry
+; GFX6-SLOWFMA-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, -1
+; GFX6-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v2, s3
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s4, s0
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s5, s1
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s3, v0
+; GFX6-SLOWFMA-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-SLOWFMA-NEXT: s_endpgm
+;
+; GFX7-LABEL: s_fdiv_f32_arcp_daz:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX7-NEXT: s_mov_b32 s7, 0xf000
+; GFX7-NEXT: s_mov_b32 s6, -1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v1, s2
+; GFX7-NEXT: s_mov_b32 s4, s0
+; GFX7-NEXT: s_mov_b32 s5, s1
+; GFX7-NEXT: v_div_scale_f32 v2, s[0:1], s3, s3, v1
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_mov_b32_e32 v0, s3
+; GFX7-NEXT: v_div_scale_f32 v0, vcc, s2, v0, s2
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v4, v0, v3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v4, v0
+; GFX7-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX7-NEXT: v_fma_f32 v0, -v2, v4, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v0, v0, v3, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v0, s3, v1
+; GFX7-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_f32_arcp_daz:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s3, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, s3
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v2, v1, s3, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_f32_arcp_daz:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v0, s4, s3, s3, s2
+; GFX10-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v0
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX10-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX10-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX10-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_div_fixup_f32 v0, v0, s3, s2
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_f32_arcp_daz:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v0, null, s3, s3, s2
+; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s2, s3, s2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v0
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX11-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX11-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_div_fixup_f32 v0, v0, s3, s2
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_f32_arcp_daz:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].W,
+; EG-NEXT: MUL_IEEE T0.X, KC0[2].Z, PS,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv arcp float %a, %b
store float %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_f32_arcp_ninf:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[2].W
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[2].Z,
-
-; GCN: v_rcp_f32_e32 [[RCP:v[0-9]+]], s{{[0-9]+}}
-; GCN: v_mul_f32_e32 [[RESULT:v[0-9]+]], s{{[0-9]+}}, [[RCP]]
-; GCN-NOT: [[RESULT]]
-; GCN: buffer_store_{{dword|b32}} [[RESULT]]
-define amdgpu_kernel void @fdiv_f32_arcp_ninf(ptr addrspace(1) %out, float %a, float %b) #0 {
+define amdgpu_kernel void @s_fdiv_f32_arcp_ninf(ptr addrspace(1) %out, float %a, float %b) #0 {
+; GFX67-LABEL: s_fdiv_f32_arcp_ninf:
+; GFX67: ; %bb.0: ; %entry
+; GFX67-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX67-NEXT: s_mov_b32 s7, 0xf000
+; GFX67-NEXT: s_mov_b32 s6, -1
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_rcp_f32_e32 v0, s3
+; GFX67-NEXT: s_mov_b32 s4, s0
+; GFX67-NEXT: s_mov_b32 s5, s1
+; GFX67-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX67-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_f32_arcp_ninf:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_rcp_f32_e32 v0, s3
+; GFX8-NEXT: v_mul_f32_e32 v2, s2, v0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_f32_arcp_ninf:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f32_e32 v0, s3
+; GFX10-NEXT: v_mul_f32_e32 v0, s2, v0
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_f32_arcp_ninf:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f32_e32 v0, s3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mov_b32 v1, 0 :: v_dual_mul_f32 v0, s2, v0
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_f32_arcp_ninf:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[2].W,
+; EG-NEXT: MUL_IEEE T0.X, PS, KC0[2].Z,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv arcp ninf float %a, %b
store float %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_v2f32:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[3].X, PS
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, KC0[2].W, PS
-
-; GCN: v_div_scale_f32
-; GCN: v_div_scale_f32
-; GCN: v_div_scale_f32
-; GCN: v_div_scale_f32
-define amdgpu_kernel void @fdiv_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+define amdgpu_kernel void @s_fdiv_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+; GFX6-FASTFMA-LABEL: s_fdiv_v2f32:
+; GFX6-FASTFMA: ; %bb.0: ; %entry
+; GFX6-FASTFMA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
+; GFX6-FASTFMA-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-FASTFMA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-FASTFMA-NEXT: s_mov_b32 s2, -1
+; GFX6-FASTFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v1, s4
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[8:9], s6, s6, v1
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v0, s6
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v0, vcc, s4, v0, s4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v0, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v4, v0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v0, -v2, v4, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v2, s5
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v0, v0, v3, v4
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[8:9], s7, s7, v2
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v0, s6, v1
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, vcc, s5, v1, s5
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v1, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v1
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v3, v5, v1
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v4, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v1, v1, s7, v2
+; GFX6-FASTFMA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-FASTFMA-NEXT: s_endpgm
+;
+; GFX6-SLOWFMA-LABEL: s_fdiv_v2f32:
+; GFX6-SLOWFMA: ; %bb.0: ; %entry
+; GFX6-SLOWFMA-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
+; GFX6-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[2:3], s6, s6, v0
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s4, v2, s4
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v4, s5
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v1, v5, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v5, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[2:3], s7, s7, v4
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v5
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, s5, v3, s5
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s2, -1
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v2
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v2, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, v1, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v1, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v2, v1, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v1, v1, s7, v4
+; GFX6-SLOWFMA-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-SLOWFMA-NEXT: s_endpgm
+;
+; GFX7-LABEL: s_fdiv_v2f32:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
+; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: s_mov_b32 s2, -1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v1, s4
+; GFX7-NEXT: v_div_scale_f32 v2, s[8:9], s6, s6, v1
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_mov_b32_e32 v0, s6
+; GFX7-NEXT: v_div_scale_f32 v0, vcc, s4, v0, s4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v4, v0, v3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v4, v0
+; GFX7-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX7-NEXT: v_fma_f32 v0, -v2, v4, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_mov_b32_e32 v2, s5
+; GFX7-NEXT: v_div_fmas_f32 v0, v0, v3, v4
+; GFX7-NEXT: v_div_scale_f32 v3, s[8:9], s7, s7, v2
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_div_fixup_f32 v0, v0, s6, v1
+; GFX7-NEXT: v_mov_b32_e32 v1, s7
+; GFX7-NEXT: v_div_scale_f32 v1, vcc, s5, v1, s5
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX7-NEXT: v_mul_f32_e32 v5, v1, v4
+; GFX7-NEXT: v_fma_f32 v6, -v3, v5, v1
+; GFX7-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX7-NEXT: v_fma_f32 v1, -v3, v5, v1
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v4, v5
+; GFX7-NEXT: v_div_fixup_f32 v1, v1, s7, v2
+; GFX7-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_v2f32:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_div_scale_f32 v1, s[2:3], s6, s6, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s4, v2, s4
+; GFX8-NEXT: v_mov_b32_e32 v4, s5
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v5, v2, v3
+; GFX8-NEXT: v_fma_f32 v6, -v1, v5, v2
+; GFX8-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX8-NEXT: v_fma_f32 v1, -v1, v5, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_scale_f32 v2, s[2:3], s7, s7, v4
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v5
+; GFX8-NEXT: v_mov_b32_e32 v3, s7
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, s5, v3, s5
+; GFX8-NEXT: v_rcp_f32_e32 v5, v2
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v1, -v2, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v1, v1, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v1
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v1, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v1, v2, v1, v5
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_div_fixup_f32 v1, v1, s7, v4
+; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_v2f32:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v0, s2, s6, s6, s4
+; GFX10-NEXT: v_div_scale_f32 v2, vcc_lo, s4, s6, s4
+; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10-NEXT: v_rcp_f32_e32 v1, v0
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX10-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX10-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX10-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_scale_f32 v2, s2, s7, s7, s5
+; GFX10-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, s5, s7, s5
+; GFX10-NEXT: v_rcp_f32_e32 v1, v2
+; GFX10-NEXT: v_div_fixup_f32 v0, v0, s6, s4
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v4, -v2, v1, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v1, v4, v1
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v1
+; GFX10-NEXT: v_fma_f32 v5, -v2, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v1
+; GFX10-NEXT: v_fma_f32 v2, -v2, v4, v3
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v1, v2, v1, v4
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: v_div_fixup_f32 v1, v1, s7, s5
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_v2f32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v0, null, s6, s6, s4
+; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s4, s6, s4
+; GFX11-NEXT: v_rcp_f32_e32 v1, v0
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX11-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX11-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_scale_f32 v2, null, s7, s7, s5
+; GFX11-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, s5, s7, s5
+; GFX11-NEXT: v_rcp_f32_e32 v1, v2
+; GFX11-NEXT: v_div_fixup_f32 v0, v0, s6, s4
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v1, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v1, v4, v1
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v1
+; GFX11-NEXT: v_fma_f32 v5, -v2, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v1
+; GFX11-NEXT: v_fma_f32 v2, -v2, v4, v3
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v1, v2, v1, v4
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: v_div_fixup_f32 v1, v1, s7, s5
+; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_v2f32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[3].Z,
+; EG-NEXT: MUL_IEEE T0.Y, KC0[3].X, PS,
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[3].Y,
+; EG-NEXT: MUL_IEEE T0.X, KC0[2].W, PS,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv <2 x float> %a, %b
store <2 x float> %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_ulp25_v2f32:
-; GCN: v_rcp_f32
-; GCN: v_rcp_f32
-; GCN-NOT: v_cmp_gt_f32
-define amdgpu_kernel void @fdiv_ulp25_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+define amdgpu_kernel void @s_fdiv_ulp25_v2f32(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+; GFX67-LABEL: s_fdiv_ulp25_v2f32:
+; GFX67: ; %bb.0: ; %entry
+; GFX67-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
+; GFX67-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX67-NEXT: v_mov_b32_e32 v0, 0x6f800000
+; GFX67-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX67-NEXT: s_mov_b32 s3, 0xf000
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_cmp_gt_f32_e64 vcc, |s6|, v0
+; GFX67-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
+; GFX67-NEXT: v_cmp_gt_f32_e64 vcc, |s7|, v0
+; GFX67-NEXT: v_mul_f32_e32 v3, s6, v2
+; GFX67-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; GFX67-NEXT: v_rcp_f32_e32 v3, v3
+; GFX67-NEXT: v_mul_f32_e32 v0, s7, v1
+; GFX67-NEXT: v_rcp_f32_e32 v4, v0
+; GFX67-NEXT: s_mov_b32 s2, -1
+; GFX67-NEXT: v_mul_f32_e32 v0, s4, v3
+; GFX67-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX67-NEXT: v_mul_f32_e32 v2, s5, v4
+; GFX67-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX67-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_ulp25_v2f32:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX8-NEXT: v_mov_b32_e32 v0, 0x6f800000
+; GFX8-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_cmp_gt_f32_e64 vcc, |s6|, v0
+; GFX8-NEXT: v_cndmask_b32_e32 v2, 1.0, v1, vcc
+; GFX8-NEXT: v_cmp_gt_f32_e64 vcc, |s7|, v0
+; GFX8-NEXT: v_mul_f32_e32 v3, s6, v2
+; GFX8-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; GFX8-NEXT: v_rcp_f32_e32 v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v0, s7, v1
+; GFX8-NEXT: v_rcp_f32_e32 v4, v0
+; GFX8-NEXT: v_mul_f32_e32 v0, s4, v3
+; GFX8-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX8-NEXT: v_mul_f32_e32 v2, s5, v4
+; GFX8-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_ulp25_v2f32:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s2, 0x6f800000, |s6|
+; GFX10-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x2f800000, s2
+; GFX10-NEXT: v_cmp_lt_f32_e64 s2, 0x6f800000, |s7|
+; GFX10-NEXT: v_mul_f32_e32 v2, s6, v0
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s2
+; GFX10-NEXT: v_rcp_f32_e32 v2, v2
+; GFX10-NEXT: v_mul_f32_e32 v3, s7, v1
+; GFX10-NEXT: v_rcp_f32_e32 v3, v3
+; GFX10-NEXT: v_mul_f32_e32 v2, s4, v2
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v2
+; GFX10-NEXT: v_mul_f32_e32 v3, s5, v3
+; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX10-NEXT: global_store_dwordx2 v4, v[0:1], s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_ulp25_v2f32:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s2, 0x6f800000, |s6|
+; GFX11-NEXT: v_cndmask_b32_e64 v0, 1.0, 0x2f800000, s2
+; GFX11-NEXT: v_cmp_lt_f32_e64 s2, 0x6f800000, |s7|
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s2
+; GFX11-NEXT: v_dual_mul_f32 v2, s6, v0 :: v_dual_mul_f32 v3, s7, v1
+; GFX11-NEXT: v_rcp_f32_e32 v2, v2
+; GFX11-NEXT: v_rcp_f32_e32 v3, v3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mul_f32 v2, s4, v2 :: v_dual_mul_f32 v3, s5, v3
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_dual_mul_f32 v0, v0, v2 :: v_dual_mul_f32 v1, v1, v3
+; GFX11-NEXT: global_store_b64 v4, v[0:1], s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_ulp25_v2f32:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[3].Z,
+; EG-NEXT: MUL_IEEE T0.Y, KC0[3].X, PS,
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[3].Y,
+; EG-NEXT: MUL_IEEE T0.X, KC0[2].W, PS,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv arcp <2 x float> %a, %b, !fpmath !0
store <2 x float> %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_v2f32_fast_math:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[3].X,
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[2].W,
-
-; GCN: v_rcp_f32
-; GCN: v_rcp_f32
-define amdgpu_kernel void @fdiv_v2f32_fast_math(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+define amdgpu_kernel void @s_fdiv_v2f32_fast_math(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+; GFX67-LABEL: s_fdiv_v2f32_fast_math:
+; GFX67: ; %bb.0: ; %entry
+; GFX67-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
+; GFX67-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX67-NEXT: s_mov_b32 s3, 0xf000
+; GFX67-NEXT: s_mov_b32 s2, -1
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_rcp_f32_e32 v0, s6
+; GFX67-NEXT: v_rcp_f32_e32 v1, s7
+; GFX67-NEXT: v_mul_f32_e32 v0, s4, v0
+; GFX67-NEXT: v_mul_f32_e32 v1, s5, v1
+; GFX67-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_v2f32_fast_math:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_rcp_f32_e32 v0, s6
+; GFX8-NEXT: v_rcp_f32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mul_f32_e32 v0, s4, v0
+; GFX8-NEXT: v_mul_f32_e32 v1, s5, v1
+; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_v2f32_fast_math:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f32_e32 v0, s6
+; GFX10-NEXT: v_rcp_f32_e32 v1, s7
+; GFX10-NEXT: v_mul_f32_e32 v0, s4, v0
+; GFX10-NEXT: v_mul_f32_e32 v1, s5, v1
+; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_v2f32_fast_math:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f32_e32 v0, s6
+; GFX11-NEXT: v_rcp_f32_e32 v1, s7
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mul_f32 v0, s4, v0 :: v_dual_mul_f32 v1, s5, v1
+; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_v2f32_fast_math:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[3].Z,
+; EG-NEXT: MUL_IEEE T0.Y, PS, KC0[3].X,
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[3].Y,
+; EG-NEXT: MUL_IEEE T0.X, PS, KC0[2].W,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv fast <2 x float> %a, %b
store <2 x float> %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_v2f32_arcp_math:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Z
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW]}}, KC0[3].Y
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[3].X,
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW]}}, PS, KC0[2].W,
-
-; GCN: v_rcp_f32
-; GCN: v_rcp_f32
-define amdgpu_kernel void @fdiv_v2f32_arcp_math(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+define amdgpu_kernel void @s_fdiv_v2f32_arcp_math(ptr addrspace(1) %out, <2 x float> %a, <2 x float> %b) #0 {
+; GFX67-LABEL: s_fdiv_v2f32_arcp_math:
+; GFX67: ; %bb.0: ; %entry
+; GFX67-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
+; GFX67-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX67-NEXT: s_mov_b32 s3, 0xf000
+; GFX67-NEXT: s_mov_b32 s2, -1
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_rcp_f32_e32 v0, s6
+; GFX67-NEXT: v_rcp_f32_e32 v1, s7
+; GFX67-NEXT: v_mul_f32_e32 v0, s4, v0
+; GFX67-NEXT: v_mul_f32_e32 v1, s5, v1
+; GFX67-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_v2f32_arcp_math:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_rcp_f32_e32 v0, s6
+; GFX8-NEXT: v_rcp_f32_e32 v1, s7
+; GFX8-NEXT: v_mov_b32_e32 v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v2, s0
+; GFX8-NEXT: v_mul_f32_e32 v0, s4, v0
+; GFX8-NEXT: v_mul_f32_e32 v1, s5, v1
+; GFX8-NEXT: flat_store_dwordx2 v[2:3], v[0:1]
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_v2f32_arcp_math:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_clause 0x1
+; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x24
+; GFX10-NEXT: v_mov_b32_e32 v2, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f32_e32 v0, s6
+; GFX10-NEXT: v_rcp_f32_e32 v1, s7
+; GFX10-NEXT: v_mul_f32_e32 v0, s4, v0
+; GFX10-NEXT: v_mul_f32_e32 v1, s5, v1
+; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[2:3]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_v2f32_arcp_math:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f32_e32 v0, s6
+; GFX11-NEXT: v_rcp_f32_e32 v1, s7
+; GFX11-NEXT: v_mov_b32_e32 v2, 0
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mul_f32 v0, s4, v0 :: v_dual_mul_f32 v1, s5, v1
+; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_v2f32_arcp_math:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[3].Z,
+; EG-NEXT: MUL_IEEE T0.Y, PS, KC0[3].X,
+; EG-NEXT: RECIP_IEEE * T0.X, KC0[3].Y,
+; EG-NEXT: MUL_IEEE T0.X, PS, KC0[2].W,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv arcp ninf <2 x float> %a, %b
store <2 x float> %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}fdiv_v4f32:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}, PS
-
-; GCN: v_div_fixup_f32
-; GCN: v_div_fixup_f32
-; GCN: v_div_fixup_f32
-; GCN: v_div_fixup_f32
-define amdgpu_kernel void @fdiv_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+define amdgpu_kernel void @s_fdiv_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+; GFX6-FASTFMA-LABEL: s_fdiv_v4f32:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-FASTFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-FASTFMA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-FASTFMA-NEXT: s_mov_b32 s10, -1
+; GFX6-FASTFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v1, s0
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[12:13], s4, s4, v1
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v0, vcc, s0, v0, s0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v0, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v4, v0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v0, -v2, v4, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v2, s1
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v0, v0, v3, v4
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[12:13], s5, s5, v2
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v0, s4, v1
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, vcc, s1, v1, s1
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v1, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v3, v5, v1
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v3, v5, v1
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v3, s2
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v4, v5
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, s[0:1], s6, s6, v3
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v1, v1, s5, v2
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v4, v6, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v4, s3
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, s[0:1], s7, s7, v4
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v6, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v2, v2, s6, v3
+; GFX6-FASTFMA-NEXT: v_mov_b32_e32 v3, s7
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s3, v3, s3
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v6, v6
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, v8, v6, v7
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v3, v3, s7, v4
+; GFX6-FASTFMA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-FASTFMA-NEXT: s_endpgm
+;
+; GFX6-SLOWFMA-LABEL: s_fdiv_v4f32:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX6-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX6-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[10:11], s4, s4, v0
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v2, s4
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s0, v2, s0
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v4, s1
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v1, v5, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v5, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[10:11], s5, s5, v4
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v5
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v3, s5
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, s1, v3, s1
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v6, s2
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s10, -1
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v2
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s4, v0
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v2, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, v1, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v7, v1, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[0:1], s6, s6, v6
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v2, v1, v5
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v2, s6
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v7, s3
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v1, v1, s5, v4
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v4, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v8, -v3, v5, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v8, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v3, v5, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[0:1], s7, s7, v7
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_mov_b32_e32 v4, s7
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, s3, v4, s3
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v2, v2, s6, v6
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v8, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v8, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v3, v3, s7, v7
+; GFX6-SLOWFMA-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-SLOWFMA-NEXT: s_endpgm
+;
+; GFX7-LABEL: s_fdiv_v4f32:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX7-NEXT: s_mov_b32 s11, 0xf000
+; GFX7-NEXT: s_mov_b32 s10, -1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_mov_b32_e32 v1, s0
+; GFX7-NEXT: v_div_scale_f32 v2, s[12:13], s4, s4, v1
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_mov_b32_e32 v0, s4
+; GFX7-NEXT: v_div_scale_f32 v0, vcc, s0, v0, s0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v4, v0, v3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v4, v0
+; GFX7-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX7-NEXT: v_fma_f32 v0, -v2, v4, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_mov_b32_e32 v2, s1
+; GFX7-NEXT: v_div_fmas_f32 v0, v0, v3, v4
+; GFX7-NEXT: v_div_scale_f32 v3, s[12:13], s5, s5, v2
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_div_fixup_f32 v0, v0, s4, v1
+; GFX7-NEXT: v_mov_b32_e32 v1, s5
+; GFX7-NEXT: v_div_scale_f32 v1, vcc, s1, v1, s1
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX7-NEXT: v_mul_f32_e32 v5, v1, v4
+; GFX7-NEXT: v_fma_f32 v6, -v3, v5, v1
+; GFX7-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX7-NEXT: v_fma_f32 v1, -v3, v5, v1
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_mov_b32_e32 v3, s2
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v4, v5
+; GFX7-NEXT: v_div_scale_f32 v4, s[0:1], s6, s6, v3
+; GFX7-NEXT: v_rcp_f32_e32 v5, v4
+; GFX7-NEXT: v_div_fixup_f32 v1, v1, s5, v2
+; GFX7-NEXT: v_mov_b32_e32 v2, s6
+; GFX7-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v6, -v4, v5, 1.0
+; GFX7-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX7-NEXT: v_mul_f32_e32 v6, v2, v5
+; GFX7-NEXT: v_fma_f32 v7, -v4, v6, v2
+; GFX7-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX7-NEXT: v_fma_f32 v2, -v4, v6, v2
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_mov_b32_e32 v4, s3
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v5, v6
+; GFX7-NEXT: v_div_scale_f32 v5, s[0:1], s7, s7, v4
+; GFX7-NEXT: v_rcp_f32_e32 v6, v5
+; GFX7-NEXT: v_div_fixup_f32 v2, v2, s6, v3
+; GFX7-NEXT: v_mov_b32_e32 v3, s7
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, s3, v3, s3
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v7, -v5, v6, 1.0
+; GFX7-NEXT: v_fma_f32 v6, v7, v6, v6
+; GFX7-NEXT: v_mul_f32_e32 v7, v3, v6
+; GFX7-NEXT: v_fma_f32 v8, -v5, v7, v3
+; GFX7-NEXT: v_fma_f32 v7, v8, v6, v7
+; GFX7-NEXT: v_fma_f32 v3, -v5, v7, v3
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v6, v7
+; GFX7-NEXT: v_div_fixup_f32 v3, v3, s7, v4
+; GFX7-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_v4f32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_div_scale_f32 v1, s[10:11], s4, s4, v0
+; GFX8-NEXT: v_mov_b32_e32 v2, s4
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s0, v2, s0
+; GFX8-NEXT: v_mov_b32_e32 v4, s1
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v5, v2, v3
+; GFX8-NEXT: v_fma_f32 v6, -v1, v5, v2
+; GFX8-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX8-NEXT: v_fma_f32 v1, -v1, v5, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_scale_f32 v2, s[10:11], s5, s5, v4
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v5
+; GFX8-NEXT: v_mov_b32_e32 v3, s5
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, s1, v3, s1
+; GFX8-NEXT: v_mov_b32_e32 v6, s2
+; GFX8-NEXT: v_rcp_f32_e32 v5, v2
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, s4, v0
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v1, -v2, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v1, v1, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v1
+; GFX8-NEXT: v_fma_f32 v7, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v7, v1, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_scale_f32 v3, s[0:1], s6, s6, v6
+; GFX8-NEXT: v_div_fmas_f32 v1, v2, v1, v5
+; GFX8-NEXT: v_mov_b32_e32 v2, s6
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s2, v2, s2
+; GFX8-NEXT: v_mov_b32_e32 v7, s3
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: v_div_fixup_f32 v1, v1, s5, v4
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v4, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v4, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v5, v2, v4
+; GFX8-NEXT: v_fma_f32 v8, -v3, v5, v2
+; GFX8-NEXT: v_fma_f32 v5, v8, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v3, v5, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_scale_f32 v3, s[0:1], s7, s7, v7
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_mov_b32_e32 v4, s7
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, s3, v4, s3
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: v_div_fixup_f32 v2, v2, s6, v6
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v8, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v8, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NEXT: v_div_fixup_f32 v3, v3, s7, v7
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_v4f32:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v0, s10, s4, s4, s0
+; GFX10-NEXT: v_div_scale_f32 v2, vcc_lo, s0, s4, s0
+; GFX10-NEXT: v_rcp_f32_e32 v1, v0
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX10-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX10-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX10-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_scale_f32 v2, s10, s5, s5, s1
+; GFX10-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX10-NEXT: v_div_scale_f32 v1, vcc_lo, s1, s5, s1
+; GFX10-NEXT: v_rcp_f32_e32 v4, v2
+; GFX10-NEXT: v_div_fixup_f32 v0, v0, s4, s0
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v3, -v2, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v3, v4
+; GFX10-NEXT: v_mul_f32_e32 v3, v1, v4
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, v1
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v4
+; GFX10-NEXT: v_fma_f32 v1, -v2, v3, v1
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_scale_f32 v2, s0, s6, s6, s2
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, s2, s6, s2
+; GFX10-NEXT: v_rcp_f32_e32 v5, v2
+; GFX10-NEXT: v_div_fixup_f32 v1, v1, s5, s1
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v4, -v2, v5, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v5, v4, v5
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v5
+; GFX10-NEXT: v_fma_f32 v6, -v2, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v6, v5
+; GFX10-NEXT: v_fma_f32 v2, -v2, v4, v3
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_scale_f32 v3, s0, s7, s7, s3
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v5, v4
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, s3, s7, s3
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: v_div_fixup_f32 v2, v2, s6, s2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: v_div_fixup_f32 v3, v3, s7, s3
+; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_v4f32:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[8:11], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v0, null, s4, s4, s0
+; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, s0, s4, s0
+; GFX11-NEXT: v_rcp_f32_e32 v1, v0
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX11-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX11-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_scale_f32 v2, null, s5, s5, s1
+; GFX11-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX11-NEXT: v_div_scale_f32 v1, vcc_lo, s1, s5, s1
+; GFX11-NEXT: v_rcp_f32_e32 v4, v2
+; GFX11-NEXT: v_div_fixup_f32 v0, v0, s4, s0
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v2, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v3, v4
+; GFX11-NEXT: v_mul_f32_e32 v3, v1, v4
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, v1
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v4
+; GFX11-NEXT: v_fma_f32 v1, -v2, v3, v1
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_scale_f32 v2, null, s6, s6, s2
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, s2, s6, s2
+; GFX11-NEXT: v_rcp_f32_e32 v5, v2
+; GFX11-NEXT: v_div_fixup_f32 v1, v1, s5, s1
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v5, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v5, v4, v5
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v5
+; GFX11-NEXT: v_fma_f32 v6, -v2, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v5
+; GFX11-NEXT: v_fma_f32 v2, -v2, v4, v3
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_scale_f32 v3, null, s7, s7, s3
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v5, v4
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, s3, s7, s3
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: v_div_fixup_f32 v2, v2, s6, s2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_div_fixup_f32 v3, v3, s7, s3
+; GFX11-NEXT: global_store_b128 v4, v[0:3], s[8:9]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_v4f32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @6
+; EG-NEXT: ALU 9, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: RECIP_IEEE * T1.W, T1.W,
+; EG-NEXT: MUL_IEEE T0.W, T0.W, PS,
+; EG-NEXT: RECIP_IEEE * T1.Z, T1.Z,
+; EG-NEXT: MUL_IEEE T0.Z, T0.Z, PS,
+; EG-NEXT: RECIP_IEEE * T1.Y, T1.Y,
+; EG-NEXT: MUL_IEEE T0.Y, T0.Y, PS,
+; EG-NEXT: RECIP_IEEE * T1.X, T1.X,
+; EG-NEXT: MUL_IEEE T0.X, T0.X, PS,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <4 x float>, ptr addrspace(1) %in, i32 1
%a = load <4 x float>, ptr addrspace(1) %in
%b = load <4 x float>, ptr addrspace(1) %b_ptr
@@ -261,21 +1947,105 @@ define amdgpu_kernel void @fdiv_v4f32(ptr addrspace(1) %out, ptr addrspace(1) %i
ret void
}
-; FUNC-LABEL: {{^}}fdiv_v4f32_fast_math:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], PS, T[0-9]+\.[XYZW]}},
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], PS, T[0-9]+\.[XYZW]}},
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], PS, T[0-9]+\.[XYZW]}},
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], PS, T[0-9]+\.[XYZW]}},
-
-; GCN: v_rcp_f32
-; GCN: v_rcp_f32
-; GCN: v_rcp_f32
-; GCN: v_rcp_f32
-define amdgpu_kernel void @fdiv_v4f32_fast_math(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+define amdgpu_kernel void @s_fdiv_v4f32_fast_math(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+; GFX67-LABEL: s_fdiv_v4f32_fast_math:
+; GFX67: ; %bb.0:
+; GFX67-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX67-NEXT: s_mov_b32 s11, 0xf000
+; GFX67-NEXT: s_mov_b32 s10, -1
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_rcp_f32_e32 v0, s4
+; GFX67-NEXT: v_rcp_f32_e32 v1, s5
+; GFX67-NEXT: v_rcp_f32_e32 v2, s6
+; GFX67-NEXT: v_rcp_f32_e32 v3, s7
+; GFX67-NEXT: v_mul_f32_e32 v0, s0, v0
+; GFX67-NEXT: v_mul_f32_e32 v1, s1, v1
+; GFX67-NEXT: v_mul_f32_e32 v2, s2, v2
+; GFX67-NEXT: v_mul_f32_e32 v3, s3, v3
+; GFX67-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_v4f32_fast_math:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_rcp_f32_e32 v0, s4
+; GFX8-NEXT: v_rcp_f32_e32 v1, s5
+; GFX8-NEXT: v_rcp_f32_e32 v2, s6
+; GFX8-NEXT: v_rcp_f32_e32 v3, s7
+; GFX8-NEXT: v_mul_f32_e32 v0, s0, v0
+; GFX8-NEXT: v_mul_f32_e32 v1, s1, v1
+; GFX8-NEXT: v_mul_f32_e32 v2, s2, v2
+; GFX8-NEXT: v_mul_f32_e32 v3, s3, v3
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_v4f32_fast_math:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f32_e32 v0, s4
+; GFX10-NEXT: v_rcp_f32_e32 v1, s5
+; GFX10-NEXT: v_rcp_f32_e32 v2, s6
+; GFX10-NEXT: v_rcp_f32_e32 v3, s7
+; GFX10-NEXT: v_mul_f32_e32 v0, s0, v0
+; GFX10-NEXT: v_mul_f32_e32 v1, s1, v1
+; GFX10-NEXT: v_mul_f32_e32 v2, s2, v2
+; GFX10-NEXT: v_mul_f32_e32 v3, s3, v3
+; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_v4f32_fast_math:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[8:11], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f32_e32 v0, s4
+; GFX11-NEXT: v_rcp_f32_e32 v1, s5
+; GFX11-NEXT: v_rcp_f32_e32 v2, s6
+; GFX11-NEXT: v_rcp_f32_e32 v3, s7
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_dual_mul_f32 v0, s0, v0 :: v_dual_mul_f32 v1, s1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mul_f32 v2, s2, v2 :: v_dual_mul_f32 v3, s3, v3
+; GFX11-NEXT: global_store_b128 v4, v[0:3], s[8:9]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_v4f32_fast_math:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @6
+; EG-NEXT: ALU 9, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: RECIP_IEEE * T1.W, T1.W,
+; EG-NEXT: MUL_IEEE T0.W, PS, T0.W,
+; EG-NEXT: RECIP_IEEE * T1.Z, T1.Z,
+; EG-NEXT: MUL_IEEE T0.Z, PS, T0.Z,
+; EG-NEXT: RECIP_IEEE * T1.Y, T1.Y,
+; EG-NEXT: MUL_IEEE T0.Y, PS, T0.Y,
+; EG-NEXT: RECIP_IEEE * T1.X, T1.X,
+; EG-NEXT: MUL_IEEE T0.X, PS, T0.X,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <4 x float>, ptr addrspace(1) %in, i32 1
%a = load <4 x float>, ptr addrspace(1) %in
%b = load <4 x float>, ptr addrspace(1) %b_ptr
@@ -284,21 +2054,105 @@ define amdgpu_kernel void @fdiv_v4f32_fast_math(ptr addrspace(1) %out, ptr addrs
ret void
}
-; FUNC-LABEL: {{^}}fdiv_v4f32_arcp_math:
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: RECIP_IEEE * T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], PS, T[0-9]+\.[XYZW]}},
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], PS, T[0-9]+\.[XYZW]}},
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], PS, T[0-9]+\.[XYZW]}},
-; R600-DAG: MUL_IEEE {{\** *}}T{{[0-9]+\.[XYZW], PS, T[0-9]+\.[XYZW]}},
-
-; GCN: v_rcp_f32
-; GCN: v_rcp_f32
-; GCN: v_rcp_f32
-; GCN: v_rcp_f32
-define amdgpu_kernel void @fdiv_v4f32_arcp_math(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+define amdgpu_kernel void @s_fdiv_v4f32_arcp_math(ptr addrspace(1) %out, ptr addrspace(1) %in) #0 {
+; GFX67-LABEL: s_fdiv_v4f32_arcp_math:
+; GFX67: ; %bb.0:
+; GFX67-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x9
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX67-NEXT: s_mov_b32 s11, 0xf000
+; GFX67-NEXT: s_mov_b32 s10, -1
+; GFX67-NEXT: s_waitcnt lgkmcnt(0)
+; GFX67-NEXT: v_rcp_f32_e32 v0, s4
+; GFX67-NEXT: v_rcp_f32_e32 v1, s5
+; GFX67-NEXT: v_rcp_f32_e32 v2, s6
+; GFX67-NEXT: v_rcp_f32_e32 v3, s7
+; GFX67-NEXT: v_mul_f32_e32 v0, s0, v0
+; GFX67-NEXT: v_mul_f32_e32 v1, s1, v1
+; GFX67-NEXT: v_mul_f32_e32 v2, s2, v2
+; GFX67-NEXT: v_mul_f32_e32 v3, s3, v3
+; GFX67-NEXT: buffer_store_dwordx4 v[0:3], off, s[8:11], 0
+; GFX67-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_v4f32_arcp_math:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX8-NEXT: v_mov_b32_e32 v4, s8
+; GFX8-NEXT: v_mov_b32_e32 v5, s9
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_rcp_f32_e32 v0, s4
+; GFX8-NEXT: v_rcp_f32_e32 v1, s5
+; GFX8-NEXT: v_rcp_f32_e32 v2, s6
+; GFX8-NEXT: v_rcp_f32_e32 v3, s7
+; GFX8-NEXT: v_mul_f32_e32 v0, s0, v0
+; GFX8-NEXT: v_mul_f32_e32 v1, s1, v1
+; GFX8-NEXT: v_mul_f32_e32 v2, s2, v2
+; GFX8-NEXT: v_mul_f32_e32 v3, s3, v3
+; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_v4f32_arcp_math:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_load_dwordx4 s[8:11], s[0:1], 0x24
+; GFX10-NEXT: v_mov_b32_e32 v4, 0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: s_load_dwordx8 s[0:7], s[10:11], 0x0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_rcp_f32_e32 v0, s4
+; GFX10-NEXT: v_rcp_f32_e32 v1, s5
+; GFX10-NEXT: v_rcp_f32_e32 v2, s6
+; GFX10-NEXT: v_rcp_f32_e32 v3, s7
+; GFX10-NEXT: v_mul_f32_e32 v0, s0, v0
+; GFX10-NEXT: v_mul_f32_e32 v1, s1, v1
+; GFX10-NEXT: v_mul_f32_e32 v2, s2, v2
+; GFX10-NEXT: v_mul_f32_e32 v3, s3, v3
+; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[8:9]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_v4f32_arcp_math:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_load_b128 s[8:11], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: s_load_b256 s[0:7], s[10:11], 0x0
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_rcp_f32_e32 v0, s4
+; GFX11-NEXT: v_rcp_f32_e32 v1, s5
+; GFX11-NEXT: v_rcp_f32_e32 v2, s6
+; GFX11-NEXT: v_rcp_f32_e32 v3, s7
+; GFX11-NEXT: v_mov_b32_e32 v4, 0
+; GFX11-NEXT: v_dual_mul_f32 v0, s0, v0 :: v_dual_mul_f32 v1, s1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_dual_mul_f32 v2, s2, v2 :: v_dual_mul_f32 v3, s3, v3
+; GFX11-NEXT: global_store_b128 v4, v[0:3], s[8:9]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_v4f32_arcp_math:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @6
+; EG-NEXT: ALU 9, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: RECIP_IEEE * T1.W, T1.W,
+; EG-NEXT: MUL_IEEE T0.W, PS, T0.W,
+; EG-NEXT: RECIP_IEEE * T1.Z, T1.Z,
+; EG-NEXT: MUL_IEEE T0.Z, PS, T0.Z,
+; EG-NEXT: RECIP_IEEE * T1.Y, T1.Y,
+; EG-NEXT: MUL_IEEE T0.Y, PS, T0.Y,
+; EG-NEXT: RECIP_IEEE * T1.X, T1.X,
+; EG-NEXT: MUL_IEEE T0.X, PS, T0.X,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <4 x float>, ptr addrspace(1) %in, i32 1
%a = load <4 x float>, ptr addrspace(1) %in
%b = load <4 x float>, ptr addrspace(1) %b_ptr
@@ -307,83 +2161,6637 @@ define amdgpu_kernel void @fdiv_v4f32_arcp_math(ptr addrspace(1) %out, ptr addrs
ret void
}
-; FUNC-LABEL: {{^}}fdiv_f32_correctly_rounded_divide_sqrt:
-
-; GCN: v_div_scale_f32 [[NUM_SCALE:v[0-9]+]]
-; GCN-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
-; GCN-DAG: v_rcp_f32_e32 [[NUM_RCP:v[0-9]+]], [[NUM_SCALE]]
-
-; PREGFX10: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX10: s_denorm_mode 15
-; GCN: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
-; PREGFX10: v_fma_f32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]], [[NUM_RCP]]
-; GFX10: v_fmac_f32_e32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]]
-; GCN: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
-; GCN: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
-; PREGFX10: v_fma_f32 [[E:v[0-9]+]], [[D]], [[B]], [[C]]
-; GFX10: v_fmac_f32_e32 [[E:v[0-9]+]], [[D]], [[B]]
-; GCN: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
-; PREGFX10: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX10: s_denorm_mode 12
-; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
-; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
-
-define amdgpu_kernel void @fdiv_f32_correctly_rounded_divide_sqrt(ptr addrspace(1) %out, float %a) #0 {
+define amdgpu_kernel void @s_fdiv_f32_correctly_rounded_divide_sqrt(ptr addrspace(1) %out, float %a) #0 {
+; GFX6-FASTFMA-LABEL: s_fdiv_f32_correctly_rounded_divide_sqrt:
+; GFX6-FASTFMA: ; %bb.0: ; %entry
+; GFX6-FASTFMA-NEXT: s_load_dword s6, s[0:1], 0xb
+; GFX6-FASTFMA-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-FASTFMA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-FASTFMA-NEXT: s_mov_b32 s2, -1
+; GFX6-FASTFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v0, s[4:5], s6, s6, 1.0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v1, v0
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, s6, 1.0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, v3, v1, v1
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v1, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v0, s6, 1.0
+; GFX6-FASTFMA-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-FASTFMA-NEXT: s_endpgm
+;
+; GFX6-SLOWFMA-LABEL: s_fdiv_f32_correctly_rounded_divide_sqrt:
+; GFX6-SLOWFMA: ; %bb.0: ; %entry
+; GFX6-SLOWFMA-NEXT: s_load_dword s4, s[0:1], 0xb
+; GFX6-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v0, s[2:3], s4, s4, 1.0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, vcc, 1.0, s4, 1.0
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s2, -1
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v2, v0
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v0, v2, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v3, v1, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v0, v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v0, -v0, v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v0, v0, v2, v3
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v0, s4, 1.0
+; GFX6-SLOWFMA-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-SLOWFMA-NEXT: s_endpgm
+;
+; GFX7-LABEL: s_fdiv_f32_correctly_rounded_divide_sqrt:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dword s6, s[0:1], 0xb
+; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: s_mov_b32 s2, -1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v0, s[4:5], s6, s6, 1.0
+; GFX7-NEXT: v_rcp_f32_e32 v1, v0
+; GFX7-NEXT: v_div_scale_f32 v2, vcc, 1.0, s6, 1.0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX7-NEXT: v_fma_f32 v1, v3, v1, v1
+; GFX7-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX7-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX7-NEXT: v_fma_f32 v3, v4, v1, v3
+; GFX7-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX7-NEXT: v_div_fixup_f32 v0, v0, s6, 1.0
+; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_f32_correctly_rounded_divide_sqrt:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v0, s[2:3], s4, s4, 1.0
+; GFX8-NEXT: v_div_scale_f32 v1, vcc, 1.0, s4, 1.0
+; GFX8-NEXT: v_rcp_f32_e32 v2, v0
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v3, -v0, v2, 1.0
+; GFX8-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX8-NEXT: v_mul_f32_e32 v3, v1, v2
+; GFX8-NEXT: v_fma_f32 v4, -v0, v3, v1
+; GFX8-NEXT: v_fma_f32 v3, v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v0, -v0, v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v0, v0, v2, v3
+; GFX8-NEXT: v_div_fixup_f32 v2, v0, s4, 1.0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_f32_correctly_rounded_divide_sqrt:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v0, s3, s2, s2, 1.0
+; GFX10-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, s2, 1.0
+; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10-NEXT: v_rcp_f32_e32 v1, v0
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX10-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX10-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX10-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_div_fixup_f32 v0, v0, s2, 1.0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_f32_correctly_rounded_divide_sqrt:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v0, null, s2, s2, 1.0
+; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, s2, 1.0
+; GFX11-NEXT: v_rcp_f32_e32 v1, v0
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v1, v3, v1
+; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX11-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX11-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_div_fixup_f32 v0, v0, s2, 1.0
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_f32_correctly_rounded_divide_sqrt:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: RECIP_IEEE * T1.X, KC0[2].Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv float 1.000000e+00, %a
store float %fdiv, ptr addrspace(1) %out
ret void
}
-
-; FUNC-LABEL: {{^}}fdiv_f32_denorms_correctly_rounded_divide_sqrt:
-
-; GCN: v_div_scale_f32 [[NUM_SCALE:v[0-9]+]]
-; GCN-DAG: v_rcp_f32_e32 [[NUM_RCP:v[0-9]+]], [[NUM_SCALE]]
-
-; PREGFX10-DAG: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
-; PREGFX10-NOT: s_setreg
-; PREGFX10: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
-; PREGFX10: v_fma_f32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]], [[NUM_RCP]]
-; PREGFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
-; PREGFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
-; PREGFX10: v_fma_f32 [[E:v[0-9]+]], [[D]], [[B]], [[C]]
-; PREGFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
-; PREGFX10-NOT: s_setreg
-
-; GFX10-NOT: s_denorm_mode
-; GFX10: v_fma_f32 [[A:v[0-9]+]], -[[NUM_SCALE]], [[NUM_RCP]], 1.0
-; GFX10: v_fmac_f32_e32 [[B:v[0-9]+]], [[A]], [[NUM_RCP]]
-; GFX10: v_div_scale_f32 [[DEN_SCALE:v[0-9]+]]
-; GFX10: v_mul_f32_e32 [[C:v[0-9]+]], [[DEN_SCALE]], [[B]]
-; GFX10: v_fma_f32 [[D:v[0-9]+]], -[[NUM_SCALE]], [[C]], [[DEN_SCALE]]
-; GFX10: v_fmac_f32_e32 [[E:v[0-9]+]], [[D]], [[B]]
-; GFX10: v_fma_f32 [[F:v[0-9]+]], -[[NUM_SCALE]], [[E]], [[DEN_SCALE]]
-; GFX10-NOT: s_denorm_mode
-
-; GCN: v_div_fmas_f32 [[FMAS:v[0-9]+]], [[F]], [[B]], [[E]]
-; GCN: v_div_fixup_f32 v{{[0-9]+}}, [[FMAS]],
-define amdgpu_kernel void @fdiv_f32_denorms_correctly_rounded_divide_sqrt(ptr addrspace(1) %out, float %a) #2 {
+define amdgpu_kernel void @s_fdiv_f32_denorms_correctly_rounded_divide_sqrt(ptr addrspace(1) %out, float %a) #1 {
+; GFX6-FASTFMA-LABEL: s_fdiv_f32_denorms_correctly_rounded_divide_sqrt:
+; GFX6-FASTFMA: ; %bb.0: ; %entry
+; GFX6-FASTFMA-NEXT: s_load_dword s6, s[0:1], 0xb
+; GFX6-FASTFMA-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-FASTFMA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-FASTFMA-NEXT: s_mov_b32 s2, -1
+; GFX6-FASTFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v0, s[4:5], s6, s6, 1.0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v1, v0
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, vcc, 1.0, s6, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, v3, v1, v1
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v1, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v0, s6, 1.0
+; GFX6-FASTFMA-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-FASTFMA-NEXT: s_endpgm
+;
+; GFX6-SLOWFMA-LABEL: s_fdiv_f32_denorms_correctly_rounded_divide_sqrt:
+; GFX6-SLOWFMA: ; %bb.0: ; %entry
+; GFX6-SLOWFMA-NEXT: s_load_dword s4, s[0:1], 0xb
+; GFX6-SLOWFMA-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-SLOWFMA-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v0, s[2:3], s4, s4, 1.0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, vcc, 1.0, s4, 1.0
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s2, -1
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v2, v0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v0, v2, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v3, v1, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v0, v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v0, -v0, v3, v1
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v0, v0, v2, v3
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v0, s4, 1.0
+; GFX6-SLOWFMA-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-SLOWFMA-NEXT: s_endpgm
+;
+; GFX7-LABEL: s_fdiv_f32_denorms_correctly_rounded_divide_sqrt:
+; GFX7: ; %bb.0: ; %entry
+; GFX7-NEXT: s_load_dword s6, s[0:1], 0xb
+; GFX7-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX7-NEXT: s_mov_b32 s3, 0xf000
+; GFX7-NEXT: s_mov_b32 s2, -1
+; GFX7-NEXT: s_waitcnt lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v0, s[4:5], s6, s6, 1.0
+; GFX7-NEXT: v_rcp_f32_e32 v1, v0
+; GFX7-NEXT: v_div_scale_f32 v2, vcc, 1.0, s6, 1.0
+; GFX7-NEXT: v_fma_f32 v3, -v0, v1, 1.0
+; GFX7-NEXT: v_fma_f32 v1, v3, v1, v1
+; GFX7-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX7-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX7-NEXT: v_fma_f32 v3, v4, v1, v3
+; GFX7-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX7-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX7-NEXT: v_div_fixup_f32 v0, v0, s6, 1.0
+; GFX7-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX7-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_fdiv_f32_denorms_correctly_rounded_divide_sqrt:
+; GFX8: ; %bb.0: ; %entry
+; GFX8-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v0, s[2:3], s4, s4, 1.0
+; GFX8-NEXT: v_div_scale_f32 v1, vcc, 1.0, s4, 1.0
+; GFX8-NEXT: v_rcp_f32_e32 v2, v0
+; GFX8-NEXT: v_fma_f32 v3, -v0, v2, 1.0
+; GFX8-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX8-NEXT: v_mul_f32_e32 v3, v1, v2
+; GFX8-NEXT: v_fma_f32 v4, -v0, v3, v1
+; GFX8-NEXT: v_fma_f32 v3, v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v0, -v0, v3, v1
+; GFX8-NEXT: v_div_fmas_f32 v0, v0, v2, v3
+; GFX8-NEXT: v_div_fixup_f32 v2, v0, s4, 1.0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: flat_store_dword v[0:1], v2
+; GFX8-NEXT: s_endpgm
+;
+; GFX10-LABEL: s_fdiv_f32_denorms_correctly_rounded_divide_sqrt:
+; GFX10: ; %bb.0: ; %entry
+; GFX10-NEXT: s_load_dword s2, s[0:1], 0x2c
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v0, s3, s2, s2, 1.0
+; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX10-NEXT: v_rcp_f32_e32 v1, v0
+; GFX10-NEXT: v_fma_f32 v2, -v0, v1, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v1, v2, v1
+; GFX10-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, s2, 1.0
+; GFX10-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX10-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX10-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX10-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX10-NEXT: v_mov_b32_e32 v1, 0
+; GFX10-NEXT: v_div_fixup_f32 v0, v0, s2, 1.0
+; GFX10-NEXT: s_waitcnt lgkmcnt(0)
+; GFX10-NEXT: global_store_dword v1, v0, s[0:1]
+; GFX10-NEXT: s_endpgm
+;
+; GFX11-LABEL: s_fdiv_f32_denorms_correctly_rounded_divide_sqrt:
+; GFX11: ; %bb.0: ; %entry
+; GFX11-NEXT: s_clause 0x1
+; GFX11-NEXT: s_load_b32 s2, s[0:1], 0x2c
+; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
+; GFX11-NEXT: s_waitcnt lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v0, null, s2, s2, 1.0
+; GFX11-NEXT: v_rcp_f32_e32 v1, v0
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v2, -v0, v1, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v1, v2, v1
+; GFX11-NEXT: v_div_scale_f32 v2, vcc_lo, 1.0, s2, 1.0
+; GFX11-NEXT: v_mul_f32_e32 v3, v2, v1
+; GFX11-NEXT: v_fma_f32 v4, -v0, v3, v2
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v1
+; GFX11-NEXT: v_fma_f32 v0, -v0, v3, v2
+; GFX11-NEXT: v_div_fmas_f32 v0, v0, v1, v3
+; GFX11-NEXT: v_mov_b32_e32 v1, 0
+; GFX11-NEXT: v_div_fixup_f32 v0, v0, s2, 1.0
+; GFX11-NEXT: global_store_b32 v1, v0, s[0:1]
+; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
+; GFX11-NEXT: s_endpgm
+;
+; EG-LABEL: s_fdiv_f32_denorms_correctly_rounded_divide_sqrt:
+; EG: ; %bb.0: ; %entry
+; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: RECIP_IEEE * T1.X, KC0[2].Z,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
entry:
%fdiv = fdiv float 1.000000e+00, %a
store float %fdiv, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}v_fdiv_f32_dynamic_denorm:
-; PREGFX10: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
-; GFX10: s_denorm_mode 15
-
-; PREGFX10: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
-; GFX10: s_denorm_mode 12
-define float @v_fdiv_f32_dynamic_denorm(float %a, float %b) #3 {
+define float @v_fdiv_f32_dynamic_denorm(float %a, float %b) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_denorm:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_denorm:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_denorm:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_denorm:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_denorm:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_denorm:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_denorm:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
%fdiv = fdiv float %a, %b
ret float %fdiv
}
-attributes #0 = { nounwind "enable-unsafe-fp-math"="false" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-features"="-flat-for-global" }
-attributes #1 = { nounwind "enable-unsafe-fp-math"="true" "denormal-fp-math-f32"="preserve-sign,preserve-sign" "target-features"="-flat-for-global" }
-attributes #2 = { nounwind "enable-unsafe-fp-math"="false" "denormal-fp-math-f32"="ieee,ieee" "target-features"="-flat-for-global" }
-attributes #3 = { nounwind "denormal-fp-math-f32"="dynamic,dynamic" "target-features"="-flat-for-global" }
+define float @v_fdiv_f32_ieee(float %x, float %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_ieee_25ulp(float %x, float %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_dynamic(float %x, float %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_dynamic_25ulp(float %x, float %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_daz(float %x, float %y) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_daz:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_daz:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_daz:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_daz:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_daz_25ulp(float %x, float %y) #0 {
+; GFX678-LABEL: v_fdiv_f32_daz_25ulp:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_mov_b32 s4, 0x6f800000
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX678-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
+; GFX678-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX678-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX678-NEXT: v_rcp_f32_e32 v1, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y, !fpmath !0
+ ret float %div
+}
+
+; If we emit an fmul, make sure it fuses into the user.
+define float @v_fdiv_f32_ieee_contractable_user(float %x, float %y, float %z) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v4
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv contract float %x, %y
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_ieee_25ulp_contractable_user(float %x, float %y, float %z) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee_25ulp_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee_25ulp_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee_25ulp_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee_25ulp_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee_25ulp_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee_25ulp_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v4
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee_25ulp_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv contract float %x, %y, !fpmath !0
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_dynamic_contractable_user(float %x, float %y, float %z) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv contract float %x, %y
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_dynamic_25ulp_contractable_user(float %x, float %y, float %z) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_25ulp_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_25ulp_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_25ulp_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv contract float %x, %y, !fpmath !0
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_daz_contractable_user(float %x, float %y, float %z) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_daz_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_daz_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_daz_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_daz_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv contract float %x, %y
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_daz_25ulp_contractable_user(float %x, float %y, float %z) #0 {
+; GFX678-LABEL: v_fdiv_f32_daz_25ulp_contractable_user:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_mov_b32 s4, 0x6f800000
+; GFX678-NEXT: v_mov_b32_e32 v3, 0x2f800000
+; GFX678-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
+; GFX678-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
+; GFX678-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX678-NEXT: v_rcp_f32_e32 v1, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX678-NEXT: v_mad_f32 v0, v3, v0, v2
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz_25ulp_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX10-NEXT: v_rcp_f32_e32 v1, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mad_f32 v0, v3, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz_25ulp_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s0
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_f32_e32 v0, v3, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz_25ulp_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv contract float %x, %y, !fpmath !0
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_ieee__nnan_ninf(float %x, float %y, float %z) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee__nnan_ninf:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee__nnan_ninf:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee__nnan_ninf:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee__nnan_ninf:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee__nnan_ninf:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee__nnan_ninf:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee__nnan_ninf:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_ieee_25ulp__nnan_ninf(float %x, float %y, float %z) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_dynamic__nnan_ninf(float %x, float %y, float %z) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic__nnan_ninf:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf(float %x, float %y, float %z) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_daz__nnan_ninf(float %x, float %y, float %z) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_daz__nnan_ninf:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_daz__nnan_ninf:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_daz__nnan_ninf:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_daz__nnan_ninf:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz__nnan_ninf:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz__nnan_ninf:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz__nnan_ninf:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_daz_25ulp__nnan_ninf(float %x, float %y, float %z) #0 {
+; GFX678-LABEL: v_fdiv_f32_daz_25ulp__nnan_ninf:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_mov_b32 s4, 0x6f800000
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX678-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
+; GFX678-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX678-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX678-NEXT: v_rcp_f32_e32 v1, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz_25ulp__nnan_ninf:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz_25ulp__nnan_ninf:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz_25ulp__nnan_ninf:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_ieee__nnan_ninf_contractable_user(float %x, float %y, float %z) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee__nnan_ninf_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee__nnan_ninf_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee__nnan_ninf_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee__nnan_ninf_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee__nnan_ninf_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee__nnan_ninf_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v4
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee__nnan_ninf_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf contract float %x, %y
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_ieee_25ulp__nnan_ninf_contractable_user(float %x, float %y, float %z) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v4
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v4
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee_25ulp__nnan_ninf_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf contract float %x, %y, !fpmath !0
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_dynamic__nnan_ninf_contractable_user(float %x, float %y, float %z) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic__nnan_ninf_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic__nnan_ninf_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic__nnan_ninf_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic__nnan_ninf_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic__nnan_ninf_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic__nnan_ninf_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf contract float %x, %y
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user(float %x, float %y, float %z) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_25ulp__nnan_ninf_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf contract float %x, %y, !fpmath !0
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_daz__nnan_ninf_contractable_user(float %x, float %y, float %z) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_daz__nnan_ninf_contractable_user:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v4, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-FASTFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_daz__nnan_ninf_contractable_user:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX6-SLOWFMA-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_daz__nnan_ninf_contractable_user:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v4, v3
+; GFX7-NEXT: v_div_scale_f32 v5, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX7-NEXT: v_fma_f32 v4, v6, v4, v4
+; GFX7-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX7-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX7-NEXT: v_fma_f32 v6, v7, v4, v6
+; GFX7-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX7-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX7-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_daz__nnan_ninf_contractable_user:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v3, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v6, -v3, v5, 1.0
+; GFX8-NEXT: v_fma_f32 v5, v6, v5, v5
+; GFX8-NEXT: v_mul_f32_e32 v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v7, -v3, v6, v4
+; GFX8-NEXT: v_fma_f32 v6, v7, v5, v6
+; GFX8-NEXT: v_fma_f32 v3, -v3, v6, v4
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v3, v3, v5, v6
+; GFX8-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX8-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz__nnan_ninf_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v3, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v4, v3
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX10-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX10-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX10-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX10-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX10-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX10-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz__nnan_ninf_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v3, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v5, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v4, v3
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v6, -v3, v4, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v4, v6, v4
+; GFX11-NEXT: v_mul_f32_e32 v6, v5, v4
+; GFX11-NEXT: v_fma_f32 v7, -v3, v6, v5
+; GFX11-NEXT: v_fmac_f32_e32 v6, v7, v4
+; GFX11-NEXT: v_fma_f32 v3, -v3, v6, v5
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v3, v3, v4, v6
+; GFX11-NEXT: v_div_fixup_f32 v0, v3, v1, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz__nnan_ninf_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf contract float %x, %y
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_f32_daz_25ulp__nnan_ninf_contractable_user(float %x, float %y, float %z) #0 {
+; GFX678-LABEL: v_fdiv_f32_daz_25ulp__nnan_ninf_contractable_user:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_mov_b32 s4, 0x6f800000
+; GFX678-NEXT: v_mov_b32_e32 v3, 0x2f800000
+; GFX678-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
+; GFX678-NEXT: v_cndmask_b32_e32 v3, 1.0, v3, vcc
+; GFX678-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX678-NEXT: v_rcp_f32_e32 v1, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX678-NEXT: v_mad_f32 v0, v3, v0, v2
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz_25ulp__nnan_ninf_contractable_user:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX10-NEXT: v_rcp_f32_e32 v1, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mad_f32 v0, v3, v0, v2
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz_25ulp__nnan_ninf_contractable_user:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
+; GFX11-NEXT: v_cndmask_b32_e64 v3, 1.0, 0x2f800000, s0
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v3
+; GFX11-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_f32_e32 v0, v3, v0
+; GFX11-NEXT: v_add_f32_e32 v0, v0, v2
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz_25ulp__nnan_ninf_contractable_user:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv nnan ninf contract float %x, %y, !fpmath !0
+ %add = fadd contract float %div, %z
+ ret float %add
+}
+
+define float @v_fdiv_neglhs_f32_ieee(float %x, float %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_neglhs_f32_ieee:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_neglhs_f32_ieee:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_neglhs_f32_ieee:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_neglhs_f32_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_neglhs_f32_ieee:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, -v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_neglhs_f32_ieee:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, -v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_neglhs_f32_ieee:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.x = fneg float %x
+ %div = fdiv float %neg.x, %y
+ ret float %div
+}
+
+define float @v_fdiv_neglhs_f32_ieee_25ulp(float %x, float %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_neglhs_f32_ieee_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_neglhs_f32_ieee_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_neglhs_f32_ieee_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_neglhs_f32_ieee_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_neglhs_f32_ieee_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, -v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_neglhs_f32_ieee_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, -v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_neglhs_f32_ieee_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.x = fneg float %x
+ %div = fdiv float %neg.x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_neglhs_f32_dynamic(float %x, float %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_neglhs_f32_dynamic:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_neglhs_f32_dynamic:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_neglhs_f32_dynamic:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_neglhs_f32_dynamic:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_neglhs_f32_dynamic:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, -v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_neglhs_f32_dynamic:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, -v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_neglhs_f32_dynamic:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.x = fneg float %x
+ %div = fdiv float %neg.x, %y
+ ret float %div
+}
+
+define float @v_fdiv_neglhs_f32_dynamic_25ulp(float %x, float %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, -v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, -v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_neglhs_f32_dynamic_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.x = fneg float %x
+ %div = fdiv float %neg.x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_neglhs_f32_daz(float %x, float %y) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_neglhs_f32_daz:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_neglhs_f32_daz:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_neglhs_f32_daz:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, -v0, v1, -v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_neglhs_f32_daz:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, -v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, -v0, v1, -v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_neglhs_f32_daz:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, -v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_neglhs_f32_daz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, -v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, -v0, v1, -v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, -v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_neglhs_f32_daz:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.x = fneg float %x
+ %div = fdiv float %neg.x, %y
+ ret float %div
+}
+
+define float @v_fdiv_neglhs_f32_daz_25ulp(float %x, float %y) #0 {
+; GFX678-LABEL: v_fdiv_neglhs_f32_daz_25ulp:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_mov_b32 s4, 0x6f800000
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX678-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
+; GFX678-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX678-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX678-NEXT: v_rcp_f32_e32 v1, v1
+; GFX678-NEXT: v_mul_f32_e64 v0, -v0, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_neglhs_f32_daz_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v1
+; GFX10-NEXT: v_mul_f32_e64 v0, -v0, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_neglhs_f32_daz_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e64 v0, -v0, v1
+; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_neglhs_f32_daz_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.x = fneg float %x
+ %div = fdiv float %neg.x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_negrhs_f32_ieee(float %x, float %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_negrhs_f32_ieee:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_negrhs_f32_ieee:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_negrhs_f32_ieee:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_negrhs_f32_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_negrhs_f32_ieee:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, -v1, -v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_negrhs_f32_ieee:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, -v1, -v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_negrhs_f32_ieee:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.y = fneg float %y
+ %div = fdiv float %x, %neg.y
+ ret float %div
+}
+
+define float @v_fdiv_negrhs_f32_ieee_25ulp(float %x, float %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_negrhs_f32_ieee_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_negrhs_f32_ieee_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_negrhs_f32_ieee_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_negrhs_f32_ieee_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_negrhs_f32_ieee_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, -v1, -v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_negrhs_f32_ieee_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, -v1, -v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_negrhs_f32_ieee_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.y = fneg float %y
+ %div = fdiv float %x, %neg.y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_negrhs_f32_dynamic(float %x, float %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_negrhs_f32_dynamic:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_negrhs_f32_dynamic:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_negrhs_f32_dynamic:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_negrhs_f32_dynamic:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_negrhs_f32_dynamic:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, -v1, -v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_negrhs_f32_dynamic:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, -v1, -v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_negrhs_f32_dynamic:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.y = fneg float %y
+ %div = fdiv float %x, %neg.y
+ ret float %div
+}
+
+define float @v_fdiv_negrhs_f32_dynamic_25ulp(float %x, float %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_negrhs_f32_dynamic_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_negrhs_f32_dynamic_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_negrhs_f32_dynamic_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_negrhs_f32_dynamic_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_negrhs_f32_dynamic_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, -v1, -v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_negrhs_f32_dynamic_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, -v1, -v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_negrhs_f32_dynamic_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.y = fneg float %y
+ %div = fdiv float %x, %neg.y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_negrhs_f32_daz(float %x, float %y) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_negrhs_f32_daz:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_negrhs_f32_daz:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_negrhs_f32_daz:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, -v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_negrhs_f32_daz:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], -v1, -v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, -v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_negrhs_f32_daz:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, -v1, -v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_negrhs_f32_daz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, -v1, -v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, -v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, -v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_negrhs_f32_daz:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.y = fneg float %y
+ %div = fdiv float %x, %neg.y
+ ret float %div
+}
+
+define float @v_fdiv_negrhs_f32_daz_25ulp(float %x, float %y) #0 {
+; GFX678-LABEL: v_fdiv_negrhs_f32_daz_25ulp:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_mov_b32 s4, 0x6f800000
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX678-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
+; GFX678-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX678-NEXT: v_mul_f32_e64 v1, -v1, v2
+; GFX678-NEXT: v_rcp_f32_e32 v1, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_negrhs_f32_daz_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e64 v1, -v1, v2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_negrhs_f32_daz_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
+; GFX11-NEXT: v_mul_f32_e64 v1, -v1, v2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_negrhs_f32_daz_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %neg.y = fneg float %y
+ %div = fdiv float %x, %neg.y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_constrhs0_ieee(float %x) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constrhs0_ieee:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_ieee:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constrhs0_ieee:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constrhs0_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constrhs0_ieee:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, 0x4640e400, 0x4640e400, v0
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constrhs0_ieee:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v0
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constrhs0_ieee:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, 12345.0
+ ret float %div
+}
+
+define float @v_fdiv_f32_constrhs0_ieee_25ulp(float %x) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constrhs0_ieee_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_ieee_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constrhs0_ieee_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constrhs0_ieee_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constrhs0_ieee_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, 0x4640e400, 0x4640e400, v0
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constrhs0_ieee_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v0
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constrhs0_ieee_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, 12345.0, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_constrhs0_dynamic(float %x) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_dynamic:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constrhs0_dynamic:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constrhs0_dynamic:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constrhs0_dynamic:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, 0x4640e400, 0x4640e400, v0
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constrhs0_dynamic:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v0
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constrhs0_dynamic:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, 12345.0
+ ret float %div
+}
+
+define float @v_fdiv_f32_constrhs0_dynamic_25ulp(float %x) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, 0x4640e400, 0x4640e400, v0
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v0
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constrhs0_dynamic_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, 12345.0, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_constrhs0_daz(float %x) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constrhs0_daz:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constrhs0_daz:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constrhs0_daz:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, v0, s6, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constrhs0_daz:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], s6, s6, v0
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, v0, s6, v0
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, s6, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constrhs0_daz:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, 0x4640e400, 0x4640e400, v0
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constrhs0_daz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, 0x4640e400, 0x4640e400, v0
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, v0, 0x4640e400, v0
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, 0x4640e400, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constrhs0_daz:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, 12345.0
+ ret float %div
+}
+
+define float @v_fdiv_f32_constrhs0_daz_25ulp(float %x) #0 {
+; GCN-LABEL: v_fdiv_f32_constrhs0_daz_25ulp:
+; GCN: ; %bb.0:
+; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GCN-NEXT: v_mul_f32_e32 v0, 0x38a9e0f0, v0
+; GCN-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constrhs0_daz_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, 12345.0, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_constlhs0_ieee(float %x) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constlhs0_ieee:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_ieee:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constlhs0_ieee:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constlhs0_ieee:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constlhs0_ieee:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x4640e400
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constlhs0_ieee:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e400
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constlhs0_ieee:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float 12345.0, %x
+ ret float %div
+}
+
+define float @v_fdiv_f32_constlhs0_ieee_25ulp(float %x) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constlhs0_ieee_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_ieee_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constlhs0_ieee_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v3, v2, v2
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constlhs0_ieee_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constlhs0_ieee_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x4640e400
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constlhs0_ieee_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e400
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v3, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v3, v2
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constlhs0_ieee_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float 12345.0, %x, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_constlhs0_dynamic(float %x) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_dynamic:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constlhs0_dynamic:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constlhs0_dynamic:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constlhs0_dynamic:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x4640e400
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constlhs0_dynamic:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e400
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constlhs0_dynamic:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float 12345.0, %x
+ ret float %div
+}
+
+define float @v_fdiv_f32_constlhs0_dynamic_25ulp(float %x) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x4640e400
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e400
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constlhs0_dynamic_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float 12345.0, %x, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_constlhs0_daz(float %x) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_constlhs0_daz:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v2, v1
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_constlhs0_daz:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v3, v1
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_constlhs0_daz:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX7-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX7-NEXT: v_rcp_f32_e32 v2, v1
+; GFX7-NEXT: v_div_scale_f32 v3, vcc, s6, v0, s6
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX7-NEXT: v_fma_f32 v2, v4, v2, v2
+; GFX7-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX7-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX7-NEXT: v_fma_f32 v4, v5, v2, v4
+; GFX7-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX7-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_constlhs0_daz:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s6, 0x4640e400
+; GFX8-NEXT: v_div_scale_f32 v1, s[4:5], v0, v0, s6
+; GFX8-NEXT: v_div_scale_f32 v2, vcc, s6, v0, s6
+; GFX8-NEXT: v_rcp_f32_e32 v3, v1
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v4, -v1, v3, 1.0
+; GFX8-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX8-NEXT: v_mul_f32_e32 v4, v2, v3
+; GFX8-NEXT: v_fma_f32 v5, -v1, v4, v2
+; GFX8-NEXT: v_fma_f32 v4, v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v1, -v1, v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v1, v1, v3, v4
+; GFX8-NEXT: v_div_fixup_f32 v0, v1, v0, s6
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constlhs0_daz:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v1, s4, v0, v0, 0x4640e400
+; GFX10-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX10-NEXT: v_rcp_f32_e32 v2, v1
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX10-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX10-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX10-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX10-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX10-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constlhs0_daz:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v1, null, v0, v0, 0x4640e400
+; GFX11-NEXT: v_div_scale_f32 v3, vcc_lo, 0x4640e400, v0, 0x4640e400
+; GFX11-NEXT: v_rcp_f32_e32 v2, v1
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v1, v2, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v2, v4, v2
+; GFX11-NEXT: v_mul_f32_e32 v4, v3, v2
+; GFX11-NEXT: v_fma_f32 v5, -v1, v4, v3
+; GFX11-NEXT: v_fmac_f32_e32 v4, v5, v2
+; GFX11-NEXT: v_fma_f32 v1, -v1, v4, v3
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v1, v1, v2, v4
+; GFX11-NEXT: v_div_fixup_f32 v0, v1, v0, 0x4640e400
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constlhs0_daz:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float 12345.0, %x
+ ret float %div
+}
+
+define float @v_fdiv_f32_constlhs0_daz_25ulp(float %x) #0 {
+; GFX678-LABEL: v_fdiv_f32_constlhs0_daz_25ulp:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_mov_b32 s4, 0x6f800000
+; GFX678-NEXT: v_mov_b32_e32 v1, 0x2f800000
+; GFX678-NEXT: v_cmp_gt_f32_e64 vcc, |v0|, s4
+; GFX678-NEXT: v_cndmask_b32_e32 v1, 1.0, v1, vcc
+; GFX678-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX678-NEXT: v_rcp_f32_e32 v0, v0
+; GFX678-NEXT: v_mul_f32_e32 v0, 0x4640e400, v0
+; GFX678-NEXT: v_mul_f32_e32 v0, v1, v0
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_constlhs0_daz_25ulp:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v0|
+; GFX10-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_rcp_f32_e32 v0, v0
+; GFX10-NEXT: v_mul_f32_e32 v0, 0x4640e400, v0
+; GFX10-NEXT: v_mul_f32_e32 v0, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_constlhs0_daz_25ulp:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v0|
+; GFX11-NEXT: v_cndmask_b32_e64 v1, 1.0, 0x2f800000, s0
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_rcp_f32_e32 v0, v0
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v0, 0x4640e400, v0
+; GFX11-NEXT: v_mul_f32_e32 v0, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_constlhs0_daz_25ulp:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float 12345.0, %x, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_ieee_nodenorm_x(float nofpclass(sub) %x, float %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee_nodenorm_x:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee_nodenorm_x:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee_nodenorm_x:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee_nodenorm_x:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee_nodenorm_x:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee_nodenorm_x:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee_nodenorm_x:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_ieee_25ulp_nodenorm_x(float nofpclass(sub) %x, float %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_x:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_x:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_x:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_x:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_x:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_x:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_x:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_dynamic_nodenorm_x(float nofpclass(sub) %x, float %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_nodenorm_x:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_dynamic_25ulp_nodenorm_x(float nofpclass(sub) %x, float %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_x:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_daz_nodenorm_x(float nofpclass(sub) %x, float %y) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_daz_nodenorm_x:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_daz_nodenorm_x:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_daz_nodenorm_x:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_daz_nodenorm_x:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz_nodenorm_x:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz_nodenorm_x:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz_nodenorm_x:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_daz_25ulp_nodenorm_x(float nofpclass(sub) %x, float %y) #0 {
+; GFX678-LABEL: v_fdiv_f32_daz_25ulp_nodenorm_x:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_mov_b32 s4, 0x6f800000
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX678-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
+; GFX678-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX678-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX678-NEXT: v_rcp_f32_e32 v1, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz_25ulp_nodenorm_x:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz_25ulp_nodenorm_x:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz_25ulp_nodenorm_x:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_ieee_nodenorm_y(float %x, float nofpclass(sub) %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee_nodenorm_y:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee_nodenorm_y:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee_nodenorm_y:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee_nodenorm_y:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee_nodenorm_y:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee_nodenorm_y:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee_nodenorm_y:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_ieee_25ulp_nodenorm_y(float %x, float nofpclass(sub) %y) #1 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_y:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_y:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_y:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v4, v3, v3
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_y:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_y:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_y:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v4, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v4, v3
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_ieee_25ulp_nodenorm_y:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_dynamic_nodenorm_y(float %x, float nofpclass(sub) %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_nodenorm_y:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_dynamic_25ulp_nodenorm_y(float %x, float nofpclass(sub) %y) #2 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_dynamic_25ulp_nodenorm_y:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y, !fpmath !0
+ ret float %div
+}
+
+define float @v_fdiv_f32_daz_nodenorm_y(float %x, float nofpclass(sub) %y) #0 {
+; GFX6-FASTFMA-LABEL: v_fdiv_f32_daz_nodenorm_y:
+; GFX6-FASTFMA: ; %bb.0:
+; GFX6-FASTFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-FASTFMA-NEXT: v_rcp_f32_e32 v3, v2
+; GFX6-FASTFMA-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX6-FASTFMA-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX6-FASTFMA-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX6-FASTFMA-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX6-FASTFMA-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX6-FASTFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-FASTFMA-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX6-FASTFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-FASTFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX6-SLOWFMA-LABEL: v_fdiv_f32_daz_nodenorm_y:
+; GFX6-SLOWFMA: ; %bb.0:
+; GFX6-SLOWFMA-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX6-SLOWFMA-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX6-SLOWFMA-NEXT: v_rcp_f32_e32 v4, v2
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX6-SLOWFMA-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX6-SLOWFMA-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX6-SLOWFMA-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX6-SLOWFMA-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX6-SLOWFMA-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX6-SLOWFMA-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX7-LABEL: v_fdiv_f32_daz_nodenorm_y:
+; GFX7: ; %bb.0:
+; GFX7-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX7-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX7-NEXT: v_rcp_f32_e32 v3, v2
+; GFX7-NEXT: v_div_scale_f32 v4, vcc, v0, v1, v0
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX7-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX7-NEXT: v_fma_f32 v3, v5, v3, v3
+; GFX7-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX7-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX7-NEXT: v_fma_f32 v5, v6, v3, v5
+; GFX7-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX7-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX7-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX7-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX7-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX8-LABEL: v_fdiv_f32_daz_nodenorm_y:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX8-NEXT: v_div_scale_f32 v2, s[4:5], v1, v1, v0
+; GFX8-NEXT: v_div_scale_f32 v3, vcc, v0, v1, v0
+; GFX8-NEXT: v_rcp_f32_e32 v4, v2
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 3
+; GFX8-NEXT: v_fma_f32 v5, -v2, v4, 1.0
+; GFX8-NEXT: v_fma_f32 v4, v5, v4, v4
+; GFX8-NEXT: v_mul_f32_e32 v5, v3, v4
+; GFX8-NEXT: v_fma_f32 v6, -v2, v5, v3
+; GFX8-NEXT: v_fma_f32 v5, v6, v4, v5
+; GFX8-NEXT: v_fma_f32 v2, -v2, v5, v3
+; GFX8-NEXT: s_setreg_imm32_b32 hwreg(HW_REG_MODE, 4, 2), 0
+; GFX8-NEXT: v_div_fmas_f32 v2, v2, v4, v5
+; GFX8-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX8-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz_nodenorm_y:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_div_scale_f32 v2, s4, v1, v1, v0
+; GFX10-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX10-NEXT: v_rcp_f32_e32 v3, v2
+; GFX10-NEXT: s_denorm_mode 15
+; GFX10-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX10-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX10-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX10-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX10-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX10-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX10-NEXT: s_denorm_mode 12
+; GFX10-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX10-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz_nodenorm_y:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_div_scale_f32 v2, null, v1, v1, v0
+; GFX11-NEXT: v_div_scale_f32 v4, vcc_lo, v0, v1, v0
+; GFX11-NEXT: v_rcp_f32_e32 v3, v2
+; GFX11-NEXT: s_denorm_mode 15
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_fma_f32 v5, -v2, v3, 1.0
+; GFX11-NEXT: v_fmac_f32_e32 v3, v5, v3
+; GFX11-NEXT: v_mul_f32_e32 v5, v4, v3
+; GFX11-NEXT: v_fma_f32 v6, -v2, v5, v4
+; GFX11-NEXT: v_fmac_f32_e32 v5, v6, v3
+; GFX11-NEXT: v_fma_f32 v2, -v2, v5, v4
+; GFX11-NEXT: s_denorm_mode 12
+; GFX11-NEXT: v_div_fmas_f32 v2, v2, v3, v5
+; GFX11-NEXT: v_div_fixup_f32 v0, v2, v1, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz_nodenorm_y:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y
+ ret float %div
+}
+
+define float @v_fdiv_f32_daz_25ulp_nodenorm_y(float %x, float nofpclass(sub) %y) #0 {
+; GFX678-LABEL: v_fdiv_f32_daz_25ulp_nodenorm_y:
+; GFX678: ; %bb.0:
+; GFX678-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX678-NEXT: s_mov_b32 s4, 0x6f800000
+; GFX678-NEXT: v_mov_b32_e32 v2, 0x2f800000
+; GFX678-NEXT: v_cmp_gt_f32_e64 vcc, |v1|, s4
+; GFX678-NEXT: v_cndmask_b32_e32 v2, 1.0, v2, vcc
+; GFX678-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX678-NEXT: v_rcp_f32_e32 v1, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX678-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX678-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX10-LABEL: v_fdiv_f32_daz_25ulp_nodenorm_y:
+; GFX10: ; %bb.0:
+; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX10-NEXT: v_cmp_lt_f32_e64 s4, 0x6f800000, |v1|
+; GFX10-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s4
+; GFX10-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX10-NEXT: v_rcp_f32_e32 v1, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX10-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX10-NEXT: s_setpc_b64 s[30:31]
+;
+; GFX11-LABEL: v_fdiv_f32_daz_25ulp_nodenorm_y:
+; GFX11: ; %bb.0:
+; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
+; GFX11-NEXT: v_cmp_lt_f32_e64 s0, 0x6f800000, |v1|
+; GFX11-NEXT: v_cndmask_b32_e64 v2, 1.0, 0x2f800000, s0
+; GFX11-NEXT: v_mul_f32_e32 v1, v1, v2
+; GFX11-NEXT: v_rcp_f32_e32 v1, v1
+; GFX11-NEXT: s_waitcnt_depctr 0xfff
+; GFX11-NEXT: v_mul_f32_e32 v0, v0, v1
+; GFX11-NEXT: v_mul_f32_e32 v0, v2, v0
+; GFX11-NEXT: s_setpc_b64 s[30:31]
+;
+; EG-LABEL: v_fdiv_f32_daz_25ulp_nodenorm_y:
+; EG: ; %bb.0:
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+ %div = fdiv float %x, %y, !fpmath !0
+ ret float %div
+}
+
+attributes #0 = { "denormal-fp-math-f32"="preserve-sign,preserve-sign" }
+attributes #1 = { "denormal-fp-math-f32"="ieee,ieee" }
+attributes #2 = { "denormal-fp-math-f32"="dynamic,dynamic" }
!0 = !{float 2.500000e+00}
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; GFX6: {{.*}}
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