[PATCH] D155329: [TableGen][CodeEmitterGen] Add support for querying operand bit offsets

[Ilya Leoshkevich via Phabricator via llvm-commits]

iii added a comment.

Hmm, yes, this indeed does not work for RISC-V. E.g., for LUI I get:

  switch (OpNum) {
  case 1:
    // op: imm20
    return 0;
  case 0:
    // op: rd
    return 20;
  }

which is in the wrong order:

  0000000000000000 <.text>:
     0:	000c72b7          	lui	t0,0xc7
  
          b7 72 0c 00  # in memory

I'll need to find (or introduce) a different criterion.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155329/new/

https://reviews.llvm.org/D155329