[PATCH] D155472: [DAG] Attempt shl narrowing in SimplifyDemandedBits (WIP)

[Simon Pilgrim via Phabricator via llvm-commits]

RKSimon created this revision.
RKSimon added reviewers: foad, pengfei, goldstein.w.n.
Herald added subscribers: StephenFan, kerbowa, asbirlea, hiraditya, jvesely, qcolombet.
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RKSimon requested review of this revision.
Herald added a project: LLVM.

Followup to D146121 <https://reviews.llvm.org/D146121>

If a shl node leaves the upper half bits zero, then see if we can profitably perform this with a half-width shl and a free zext.

I'm still triaging the remaining regressions, but wanted to publish the WIP patch to show the current effects on codegen.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155472

Files:
  llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp
  llvm/test/CodeGen/AMDGPU/amdgpu-codegenprepare-idiv.ll
  llvm/test/CodeGen/AMDGPU/branch-folding-implicit-def-subreg.ll
  llvm/test/CodeGen/AMDGPU/collapse-endcf.ll
  llvm/test/CodeGen/AMDGPU/idiv-licm.ll
  llvm/test/CodeGen/AMDGPU/promote-constOffset-to-imm.ll
  llvm/test/CodeGen/AMDGPU/spill-scavenge-offset.ll
  llvm/test/CodeGen/AMDGPU/waitcnt-vscnt.ll
  llvm/test/CodeGen/X86/2009-05-30-ISelBug.ll
  llvm/test/CodeGen/X86/atomic-rm-bit-test-64.ll
  llvm/test/CodeGen/X86/avx512vnni-combine.ll
  llvm/test/CodeGen/X86/avxvnni-combine.ll
  llvm/test/CodeGen/X86/bswap.ll
  llvm/test/CodeGen/X86/bt.ll
  llvm/test/CodeGen/X86/buildvec-insertvec.ll
  llvm/test/CodeGen/X86/cmp-concat.ll
  llvm/test/CodeGen/X86/combine-bitreverse.ll
  llvm/test/CodeGen/X86/const-shift-of-constmasked.ll
  llvm/test/CodeGen/X86/dagcombine-shifts.ll
  llvm/test/CodeGen/X86/divmod128.ll
  llvm/test/CodeGen/X86/extract-bits.ll
  llvm/test/CodeGen/X86/fp128-i128.ll
  llvm/test/CodeGen/X86/lea-dagdag.ll
  llvm/test/CodeGen/X86/lea-opt2.ll
  llvm/test/CodeGen/X86/lsr-loop-exit-cond.ll
  llvm/test/CodeGen/X86/masked_compressstore.ll
  llvm/test/CodeGen/X86/masked_expandload.ll
  llvm/test/CodeGen/X86/or-address.ll
  llvm/test/CodeGen/X86/parity.ll
  llvm/test/CodeGen/X86/pr22970.ll
  llvm/test/CodeGen/X86/pr38217.ll
  llvm/test/CodeGen/X86/pr62653.ll
  llvm/test/CodeGen/X86/select.ll
  llvm/test/CodeGen/X86/select_const.ll
  llvm/test/CodeGen/X86/selectcc-to-shiftand.ll
  llvm/test/CodeGen/X86/setcc.ll
  llvm/test/CodeGen/X86/shift-combine.ll
  llvm/test/CodeGen/X86/shift-pair.ll
  llvm/test/CodeGen/X86/vector-shuffle-variable-128.ll
  llvm/test/CodeGen/X86/vector-shuffle-variable-256.ll
  llvm/test/CodeGen/X86/vselect.ll
  llvm/test/CodeGen/X86/zext-logicop-shift-load.ll
  llvm/test/CodeGen/X86/zext-shl.ll

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