[PATCH] D155433: [RISCV] Add SDNode patterns for vandn.[vv,vx]

[Luke Lau via Phabricator via llvm-commits]

luke added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td:239
+                                 (not vti.ScalarRegClass:$rs1)),
+                               vti.RegClass:$rs2)),
+              (!cast<Instruction>("PseudoVANDN_VX_"#vti.LMul.MX)
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I'm only matching this scalar form here, although there's another way of representing it that could be canonicalised: https://github.com/llvm/llvm-project/issues/63868


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155433/new/

https://reviews.llvm.org/D155433