[PATCH] D153499: [RISCV] Add support for custom CSRs for Sifive S76.

[Zixuan Wu via Phabricator via llvm-commits]

zixuan-wu added inline comments.


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Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:1839
+    auto CheckCSREncodingConflict = [&]() {
+      auto Reg = RISCVSysReg::lookupSiFiveRegByEncoding(SysReg->Encoding);
+      if (Reg && Reg->haveVendorRequiredFeatures(getSTI().getFeatureBits())) {
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Could this move forward more?  Constructing more abstract infra to support all vendor reg instead of just SiFive.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153499/new/

https://reviews.llvm.org/D153499