[PATCH] D155391: [RISCV] Use RISCVISD::CZERO_EQZ/CZERO_NEZ for XVentanaCondOps.

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/test/CodeGen/RISCV/condops.ll:1294
 ; RV64XVENTANACONDOPS-NEXT:    slt a0, a0, a1
-; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a2, a0
-; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a3, a0
+; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, 1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a3, a0
----------------
wangpc wrote:
> Regression here? (though it is the same as `zicond`).
Yes. D155328 should fix it.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155391/new/

https://reviews.llvm.org/D155391