[PATCH] D155391: [RISCV] Use RISCVISD::CZERO_EQZ/CZERO_NEZ for XVentanaCondOps.

[Wang Pengcheng via Phabricator via llvm-commits]

wangpc added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:5902
 
-  // When Zicond is present, emit CZERO_EQZ and CZERO_NEZ nodes to implement
-  // the SELECT. Performing the lowering here allows for greater control over
-  // when CZERO_{EQZ/NEZ} are used vs another branchless sequence or
-  // RISCVISD::SELECT_CC node (branch-based select).
-  if (Subtarget.hasStdExtZicond() && VT.isScalarInteger()) {
+  // When Zicond or rXVentanaCondOps is present, emit CZERO_EQZ and CZERO_NEZ
+  // nodes to implement the SELECT. Performing the lowering here allows for
----------------
Typo: `rXVentanaCondOps`->`XVentanaCondOps`


================
Comment at: llvm/test/CodeGen/RISCV/condops.ll:1294
 ; RV64XVENTANACONDOPS-NEXT:    slt a0, a0, a1
-; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a2, a0
-; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a3, a0
+; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, 1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a3, a0
----------------
Regression here? (though it is the same as `zicond`).


================
Comment at: llvm/test/CodeGen/RISCV/condops.ll:1442
 ; RV64XVENTANACONDOPS-NEXT:    slt a0, a1, a0
-; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a2, a0
-; RV64XVENTANACONDOPS-NEXT:    vt.maskc a0, a3, a0
+; RV64XVENTANACONDOPS-NEXT:    xori a0, a0, 1
+; RV64XVENTANACONDOPS-NEXT:    vt.maskcn a1, a3, a0
----------------
ditto.


Repository:
  rG LLVM Github Monorepo

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  https://reviews.llvm.org/D155391/new/

https://reviews.llvm.org/D155391