[llvm] a41e7a2 - [tests] precommit tests for D155350

[via llvm-commits]

Author: zhongyunde
Date: 2023-07-15T19:36:37+08:00
New Revision: a41e7a2a5db8be9f59f6e7e4aa1bf22c4b62e41c

URL: https://github.com/llvm/llvm-project/commit/a41e7a2a5db8be9f59f6e7e4aa1bf22c4b62e41c
DIFF: https://github.com/llvm/llvm-project/commit/a41e7a2a5db8be9f59f6e7e4aa1bf22c4b62e41c.diff

LOG: [tests] precommit tests for D155350

Reviewed By: nikic
Differential Revision: https://reviews.llvm.org/D155363

Added: 
    

Modified: 
    llvm/test/Transforms/InstCombine/rem-mul-shl.ll

Removed: 
    


################################################################################
diff  --git a/llvm/test/Transforms/InstCombine/rem-mul-shl.ll b/llvm/test/Transforms/InstCombine/rem-mul-shl.ll
index e16da2d684ee50..fae4c8e38a57cb 100644
--- a/llvm/test/Transforms/InstCombine/rem-mul-shl.ll
+++ b/llvm/test/Transforms/InstCombine/rem-mul-shl.ll
@@ -1,6 +1,7 @@
 ; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
 ; RUN: opt < %s -passes=instcombine -S | FileCheck %s
 declare void @use8(i8)
+declare i64 @llvm.vscale.i64()
 
 define i8 @srem_non_matching(i8 %X, i8 %Y) {
 ; CHECK-LABEL: @srem_non_matching(
@@ -825,3 +826,56 @@ define i8 @urem_shl_XX_mul_XX(i8 %X) {
   %r = urem i8 %BO0, %BO1
   ret i8 %r
 }
+
+; Negative test: No attribute vscale_range to indicate range
+define i64 @urem_shl_vscale() {
+; CHECK-LABEL: @urem_shl_vscale(
+; CHECK-NEXT:    [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT:    [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 2
+; CHECK-NEXT:    [[REM:%.*]] = urem i64 1024, [[SHIFT]]
+; CHECK-NEXT:    ret i64 [[REM]]
+;
+  %vscale = call i64 @llvm.vscale.i64()
+  %shift = shl nuw nsw i64 %vscale, 2
+  %rem = urem i64 1024, %shift
+  ret i64 %rem
+}
+
+define i64 @urem_shl_vscale_range() vscale_range(1,16) {
+; CHECK-LABEL: @urem_shl_vscale_range(
+; CHECK-NEXT:    [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT:    [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 2
+; CHECK-NEXT:    [[REM:%.*]] = urem i64 1024, [[SHIFT]]
+; CHECK-NEXT:    ret i64 [[REM]]
+;
+  %vscale = call i64 @llvm.vscale.i64()
+  %shift = shl nuw nsw i64 %vscale, 2
+  %rem = urem i64 1024, %shift
+  ret i64 %rem
+}
+
+define i64 @urem_vscale_range() vscale_range(1,16) {
+; CHECK-LABEL: @urem_vscale_range(
+; CHECK-NEXT:    [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT:    [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 2
+; CHECK-NEXT:    [[REM:%.*]] = urem i64 1024, [[SHIFT]]
+; CHECK-NEXT:    ret i64 [[REM]]
+;
+  %vscale = call i64 @llvm.vscale.i64()
+  %shift = shl nuw nsw i64 %vscale, 2
+  %rem = urem i64 1024, %shift
+  ret i64 %rem
+}
+
+define i64 @urem_shl_vscale_out_of_range() vscale_range(1,16) {
+; CHECK-LABEL: @urem_shl_vscale_out_of_range(
+; CHECK-NEXT:    [[VSCALE:%.*]] = call i64 @llvm.vscale.i64()
+; CHECK-NEXT:    [[SHIFT:%.*]] = shl nuw nsw i64 [[VSCALE]], 20
+; CHECK-NEXT:    [[REM:%.*]] = urem i64 1024, [[SHIFT]]
+; CHECK-NEXT:    ret i64 [[REM]]
+;
+  %vscale = call i64 @llvm.vscale.i64()
+  %shift = shl nuw nsw i64 %vscale, 20
+  %rem = urem i64 1024, %shift
+  ret i64 %rem
+}