[llvm] 6a35cea - [RISCV][GlobalISel] Legalize add, sub and binary logical instructions for narrow types
Nitin John Raj via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 14 18:28:22 PDT 2023
Author: Nitin John Raj
Date: 2023-07-14T18:22:53-07:00
New Revision: 6a35ceaacf06a5fcaf649d4f63600a79b365e103
URL: https://github.com/llvm/llvm-project/commit/6a35ceaacf06a5fcaf649d4f63600a79b365e103
DIFF: https://github.com/llvm/llvm-project/commit/6a35ceaacf06a5fcaf649d4f63600a79b365e103.diff
LOG: [RISCV][GlobalISel] Legalize add, sub and binary logical instructions for narrow types
For rv32, we test the legalization of i8, i16 and i32. For rv64, we additionally test the legalization of i64.
This is the first of a series of commits aiming to legalize arithmetic instructions for RISCV.
Reviewed By: craig.topper, arsenm
Differential Revision: https://reviews.llvm.org/D154978
Added:
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-or.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-xor.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-and.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-or.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-xor.mir
Modified:
llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
index f6a75b9c028103..3f829cc2e6773d 100644
--- a/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
+++ b/llvm/lib/Target/RISCV/GISel/RISCVLegalizerInfo.cpp
@@ -11,6 +11,7 @@
//===----------------------------------------------------------------------===//
#include "RISCVLegalizerInfo.h"
+#include "RISCVSubtarget.h"
#include "llvm/CodeGen/TargetOpcodes.h"
#include "llvm/CodeGen/ValueTypes.h"
#include "llvm/IR/DerivedTypes.h"
@@ -19,5 +20,14 @@
using namespace llvm;
RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
+ const unsigned XLen = ST.getXLen();
+ const LLT XLenLLT = LLT::scalar(XLen);
+
+ using namespace TargetOpcode;
+
+ getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
+ .legalFor({XLenLLT})
+ .clampScalar(0, XLenLLT, XLenLLT);
+
getLegacyLegalizerInfo().computeTables();
}
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir
new file mode 100644
index 00000000000000..fc89ec885bd34e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-add.mir
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: add_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: add_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
+ ; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s32)
+ %3:_(s8) = G_TRUNC %1(s32)
+ %4:_(s8) = G_ADD %3, %4
+ %5:_(s32) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: add_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: add_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[ADD]]
+ ; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s32)
+ %3:_(s16) = G_TRUNC %1(s32)
+ %4:_(s16) = G_ADD %3, %4
+ %5:_(s32) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: add_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: add_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s32) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[ADD]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_ADD %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir
new file mode 100644
index 00000000000000..7f4c15ed30fb6f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-and.mir
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: and_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: and_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[AND]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s32)
+ %3:_(s8) = G_TRUNC %1(s32)
+ %4:_(s8) = G_AND %3, %4
+ %5:_(s32) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: and_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: and_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[AND]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s32)
+ %3:_(s16) = G_TRUNC %1(s32)
+ %4:_(s16) = G_AND %3, %4
+ %5:_(s32) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: and_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: and_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s32) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_AND %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-or.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-or.mir
new file mode 100644
index 00000000000000..b953fc22c4e0ef
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-or.mir
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: or_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: or_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[OR]]
+ ; CHECK-NEXT: $x10 = COPY [[OR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s32)
+ %3:_(s8) = G_TRUNC %1(s32)
+ %4:_(s8) = G_OR %3, %4
+ %5:_(s32) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: or_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: or_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[OR]]
+ ; CHECK-NEXT: $x10 = COPY [[OR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s32)
+ %3:_(s16) = G_TRUNC %1(s32)
+ %4:_(s16) = G_OR %3, %4
+ %5:_(s32) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: or_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: or_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s32) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[OR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_OR %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir
new file mode 100644
index 00000000000000..52004e44e634fb
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-sub.mir
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: sub_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: sub_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[SUB]]
+ ; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s32)
+ %3:_(s8) = G_TRUNC %1(s32)
+ %4:_(s8) = G_SUB %3, %4
+ %5:_(s32) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: sub_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: sub_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[SUB]]
+ ; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s32)
+ %3:_(s16) = G_TRUNC %1(s32)
+ %4:_(s16) = G_SUB %3, %4
+ %5:_(s32) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: sub_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: sub_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s32) = G_SUB [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[SUB]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_SUB %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-xor.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-xor.mir
new file mode 100644
index 00000000000000..e6863b7207cad7
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv32/legalize-xor.mir
@@ -0,0 +1,58 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv32 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: xor_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: xor_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[XOR]]
+ ; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s32)
+ %3:_(s8) = G_TRUNC %1(s32)
+ %4:_(s8) = G_XOR %3, %4
+ %5:_(s32) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: xor_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: xor_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[XOR]]
+ ; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s32)
+ %3:_(s16) = G_TRUNC %1(s32)
+ %4:_(s16) = G_XOR %3, %4
+ %5:_(s32) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s32)
+ PseudoRET implicit $x10
+
+...
+---
+name: xor_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: xor_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s32) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s32) = COPY $x11
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s32) = G_XOR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[XOR]](s32)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s32) = COPY $x10
+ %1:_(s32) = COPY $x11
+ %2:_(s32) = G_XOR %0, %1
+ $x10 = COPY %2(s32)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
new file mode 100644
index 00000000000000..b96e0ec8ed9842
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-add.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: add_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: add_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ADD]]
+ ; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_ADD %3, %4
+ %5:_(s64) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: add_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: add_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ADD]]
+ ; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s64)
+ %3:_(s16) = G_TRUNC %1(s64)
+ %4:_(s16) = G_ADD %3, %4
+ %5:_(s64) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: add_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: add_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[ADD]]
+ ; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s32) = G_TRUNC %0(s64)
+ %3:_(s32) = G_TRUNC %1(s64)
+ %4:_(s32) = G_ADD %3, %4
+ %5:_(s64) = G_ANYEXT %4(s32)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: add_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: add_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[ADD:%[0-9]+]]:_(s64) = G_ADD [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[ADD]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s64) = G_ADD %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-and.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-and.mir
new file mode 100644
index 00000000000000..c04daeb7e1590e
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-and.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: and_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: and_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[AND]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_AND %3, %4
+ %5:_(s64) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: and_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: and_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[AND]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s64)
+ %3:_(s16) = G_TRUNC %1(s64)
+ %4:_(s16) = G_AND %3, %4
+ %5:_(s64) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: and_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: and_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[AND]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s32) = G_TRUNC %0(s64)
+ %3:_(s32) = G_TRUNC %1(s64)
+ %4:_(s32) = G_AND %3, %4
+ %5:_(s64) = G_ANYEXT %4(s32)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: and_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: and_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[AND:%[0-9]+]]:_(s64) = G_AND [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[AND]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s64) = G_AND %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-or.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-or.mir
new file mode 100644
index 00000000000000..9a7a234a55687f
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-or.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: or_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: or_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[OR]]
+ ; CHECK-NEXT: $x10 = COPY [[OR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_OR %3, %4
+ %5:_(s64) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: or_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: or_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[OR]]
+ ; CHECK-NEXT: $x10 = COPY [[OR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s64)
+ %3:_(s16) = G_TRUNC %1(s64)
+ %4:_(s16) = G_OR %3, %4
+ %5:_(s64) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: or_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: or_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[OR]]
+ ; CHECK-NEXT: $x10 = COPY [[OR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s32) = G_TRUNC %0(s64)
+ %3:_(s32) = G_TRUNC %1(s64)
+ %4:_(s32) = G_OR %3, %4
+ %5:_(s64) = G_ANYEXT %4(s32)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: or_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: or_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[OR:%[0-9]+]]:_(s64) = G_OR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[OR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s64) = G_OR %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
new file mode 100644
index 00000000000000..010b0b6f8ef880
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-sub.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: sub_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: sub_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[SUB]]
+ ; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_SUB %3, %4
+ %5:_(s64) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sub_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: sub_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[SUB]]
+ ; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s64)
+ %3:_(s16) = G_TRUNC %1(s64)
+ %4:_(s16) = G_SUB %3, %4
+ %5:_(s64) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sub_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: sub_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[SUB]]
+ ; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s32) = G_TRUNC %0(s64)
+ %3:_(s32) = G_TRUNC %1(s64)
+ %4:_(s32) = G_SUB %3, %4
+ %5:_(s64) = G_ANYEXT %4(s32)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: sub_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: sub_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[SUB:%[0-9]+]]:_(s64) = G_SUB [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[SUB]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s64) = G_SUB %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
diff --git a/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-xor.mir b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-xor.mir
new file mode 100644
index 00000000000000..461821631dcf00
--- /dev/null
+++ b/llvm/test/CodeGen/RISCV/GlobalISel/legalizer/rv64/legalize-xor.mir
@@ -0,0 +1,77 @@
+# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
+# RUN: llc -mtriple=riscv64 -run-pass=legalizer %s -o - \
+# RUN: | FileCheck %s
+---
+name: xor_i8
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: xor_i8
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[XOR]]
+ ; CHECK-NEXT: $x10 = COPY [[XOR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s8) = G_TRUNC %0(s64)
+ %3:_(s8) = G_TRUNC %1(s64)
+ %4:_(s8) = G_XOR %3, %4
+ %5:_(s64) = G_ANYEXT %4(s8)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: xor_i16
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: xor_i16
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[XOR]]
+ ; CHECK-NEXT: $x10 = COPY [[XOR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s16) = G_TRUNC %0(s64)
+ %3:_(s16) = G_TRUNC %1(s64)
+ %4:_(s16) = G_XOR %3, %4
+ %5:_(s64) = G_ANYEXT %4(s16)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: xor_i32
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: xor_i32
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[XOR]]
+ ; CHECK-NEXT: $x10 = COPY [[XOR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s32) = G_TRUNC %0(s64)
+ %3:_(s32) = G_TRUNC %1(s64)
+ %4:_(s32) = G_XOR %3, %4
+ %5:_(s64) = G_ANYEXT %4(s32)
+ $x10 = COPY %5(s64)
+ PseudoRET implicit $x10
+
+...
+---
+name: xor_i64
+body: |
+ bb.0.entry:
+ ; CHECK-LABEL: name: xor_i64
+ ; CHECK: [[COPY:%[0-9]+]]:_(s64) = COPY $x10
+ ; CHECK-NEXT: [[COPY1:%[0-9]+]]:_(s64) = COPY $x11
+ ; CHECK-NEXT: [[XOR:%[0-9]+]]:_(s64) = G_XOR [[COPY]], [[COPY1]]
+ ; CHECK-NEXT: $x10 = COPY [[XOR]](s64)
+ ; CHECK-NEXT: PseudoRET implicit $x10
+ %0:_(s64) = COPY $x10
+ %1:_(s64) = COPY $x11
+ %2:_(s64) = G_XOR %0, %1
+ $x10 = COPY %2(s64)
+ PseudoRET implicit $x10
+
+...
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