[llvm] 21ca892 - [NFC][AMDGPU] Add automated tests in or.ll
Konstantina Mitropoulou via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 14 12:39:49 PDT 2023
Author: Konstantina Mitropoulou
Date: 2023-07-14T12:39:14-07:00
New Revision: 21ca892f698ac59e86ede6e4a2d4d747b0a36ae8
URL: https://github.com/llvm/llvm-project/commit/21ca892f698ac59e86ede6e4a2d4d747b0a36ae8
DIFF: https://github.com/llvm/llvm-project/commit/21ca892f698ac59e86ede6e4a2d4d747b0a36ae8.diff
LOG: [NFC][AMDGPU] Add automated tests in or.ll
Reviewed By: arsenm
Differential Revision: https://reviews.llvm.org/D155265
Added:
Modified:
llvm/test/CodeGen/AMDGPU/or.ll
Removed:
################################################################################
diff --git a/llvm/test/CodeGen/AMDGPU/or.ll b/llvm/test/CodeGen/AMDGPU/or.ll
index 8f82a53cafe10f..74969a68dd5756 100644
--- a/llvm/test/CodeGen/AMDGPU/or.ll
+++ b/llvm/test/CodeGen/AMDGPU/or.ll
@@ -1,15 +1,64 @@
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=SI -check-prefix=FUNC %s
-; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG -check-prefix=FUNC %s
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 3
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=verde -verify-machineinstrs < %s | FileCheck -check-prefix=GFX6 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck -check-prefix=GFX8 %s
+; RUN: llc -amdgpu-scalarize-global-loads=false -march=r600 -mcpu=redwood < %s | FileCheck -check-prefix=EG %s
-
-; FUNC-LABEL: {{^}}or_v2i32:
-; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
define amdgpu_kernel void @or_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+; GFX6-LABEL: or_v2i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: or_v2i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: s_mov_b32 s10, s6
+; GFX8-NEXT: s_mov_b32 s11, s7
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s2
+; GFX8-NEXT: s_mov_b32 s9, s3
+; GFX8-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s4, s0
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v3
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v2
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: or_v2i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: OR_INT * T0.Y, T0.Y, T0.W,
+; EG-NEXT: OR_INT T0.X, T0.X, T0.Z,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <2 x i32>, ptr addrspace(1) %in, i32 1
%a = load <2 x i32>, ptr addrspace(1) %in
%b = load <2 x i32>, ptr addrspace(1) %b_ptr
@@ -18,17 +67,71 @@ define amdgpu_kernel void @or_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in)
ret void
}
-; FUNC-LABEL: {{^}}or_v4i32:
-; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-; EG: OR_INT {{\*? *}}T{{[0-9]+\.[XYZW], T[0-9]+\.[XYZW], T[0-9]+\.[XYZW]}}
-
-; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
-; SI: v_or_b32_e32 v{{[0-9]+, v[0-9]+, v[0-9]+}}
define amdgpu_kernel void @or_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in) {
+; GFX6-LABEL: or_v4i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; GFX6-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX6-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX6-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX6-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX6-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: or_v4i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: s_mov_b32 s10, s6
+; GFX8-NEXT: s_mov_b32 s11, s7
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s2
+; GFX8-NEXT: s_mov_b32 s9, s3
+; GFX8-NEXT: buffer_load_dwordx4 v[0:3], off, s[8:11], 0
+; GFX8-NEXT: buffer_load_dwordx4 v[4:7], off, s[8:11], 0 offset:16
+; GFX8-NEXT: s_mov_b32 s4, s0
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v3, v3, v7
+; GFX8-NEXT: v_or_b32_e32 v2, v2, v6
+; GFX8-NEXT: v_or_b32_e32 v1, v1, v5
+; GFX8-NEXT: v_or_b32_e32 v0, v0, v4
+; GFX8-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: or_v4i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @6
+; EG-NEXT: ALU 5, @11, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_128 T1.XYZW, T0.X, 16, #1
+; EG-NEXT: VTX_READ_128 T0.XYZW, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 11:
+; EG-NEXT: OR_INT * T0.W, T0.W, T1.W,
+; EG-NEXT: OR_INT * T0.Z, T0.Z, T1.Z,
+; EG-NEXT: OR_INT * T0.Y, T0.Y, T1.Y,
+; EG-NEXT: OR_INT T0.X, T0.X, T1.X,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%b_ptr = getelementptr <4 x i32>, ptr addrspace(1) %in, i32 1
%a = load <4 x i32>, ptr addrspace(1) %in
%b = load <4 x i32>, ptr addrspace(1) %b_ptr
@@ -37,52 +140,263 @@ define amdgpu_kernel void @or_v4i32(ptr addrspace(1) %out, ptr addrspace(1) %in)
ret void
}
-; FUNC-LABEL: {{^}}scalar_or_i32:
-; SI: s_or_b32
define amdgpu_kernel void @scalar_or_i32(ptr addrspace(1) %out, i32 %a, i32 %b) {
+; GFX6-LABEL: scalar_or_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_or_b32 s0, s2, s3
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: scalar_or_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s4, s0
+; GFX8-NEXT: s_or_b32 s0, s2, s3
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: scalar_or_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T1.X, KC0[2].Z, KC0[2].W,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%or = or i32 %a, %b
store i32 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}vector_or_i32:
-; SI: v_or_b32_e32 v{{[0-9]}}
define amdgpu_kernel void @vector_or_i32(ptr addrspace(1) %out, ptr addrspace(1) %a, i32 %b) {
+; GFX6-LABEL: vector_or_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_load_dword s12, s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_mov_b32 s10, s2
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s6
+; GFX6-NEXT: s_mov_b32 s9, s7
+; GFX6-NEXT: s_mov_b32 s11, s3
+; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v0, s12, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: vector_or_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX8-NEXT: s_load_dword s12, s[0:1], 0x34
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_mov_b32 s10, s2
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s6
+; GFX8-NEXT: s_mov_b32 s9, s7
+; GFX8-NEXT: s_mov_b32 s11, s3
+; GFX8-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s0, s4
+; GFX8-NEXT: s_mov_b32 s1, s5
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, s12, v0
+; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: vector_or_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: OR_INT T0.X, T0.X, KC0[2].W,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%loada = load i32, ptr addrspace(1) %a
%or = or i32 %loada, %b
store i32 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}scalar_or_literal_i32:
-; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x1869f
define amdgpu_kernel void @scalar_or_literal_i32(ptr addrspace(1) %out, i32 %a) {
+; GFX6-LABEL: scalar_or_literal_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s4, s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_or_b32 s4, s4, 0x1869f
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: scalar_or_literal_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dword s4, s[0:1], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_or_b32 s4, s4, 0x1869f
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: scalar_or_literal_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: LSHR T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T1.X, KC0[2].Z, literal.y,
+; EG-NEXT: 2(2.802597e-45), 99999(1.401284e-40)
%or = or i32 %a, 99999
store i32 %or, ptr addrspace(1) %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}scalar_or_literal_i64:
-; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
-; SI-DAG: s_or_b32 s[[RES_HI:[0-9]+]], s[[HI]], 0xf237b
-; SI-DAG: s_or_b32 s[[RES_LO:[0-9]+]], s[[LO]], 0x3039
-; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_LO]]
-; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, s[[RES_HI]]
define amdgpu_kernel void @scalar_or_literal_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
+; GFX6-LABEL: scalar_or_literal_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x13
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_or_b32 s5, s5, 0xf237b
+; GFX6-NEXT: s_or_b32 s4, s4, 0x3039
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: scalar_or_literal_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x4c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_or_b32 s5, s5, 0xf237b
+; GFX8-NEXT: s_or_b32 s4, s4, 0x3039
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: scalar_or_literal_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: OR_INT * T0.Y, KC0[5].X, literal.x,
+; EG-NEXT: 992123(1.390260e-39), 0(0.000000e+00)
+; EG-NEXT: OR_INT T0.X, KC0[4].W, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 12345(1.729903e-41), 2(2.802597e-45)
%or = or i64 %a, 4261135838621753
store i64 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}scalar_or_literal_multi_use_i64:
-; SI: s_load_dwordx2 s[[[LO:[0-9]+]]:[[HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
-; SI-DAG: s_mov_b32 s[[K_HI:[0-9]+]], 0xf237b
-; SI-DAG: s_movk_i32 s[[K_LO:[0-9]+]], 0x3039
-; SI: s_or_b64 s{{\[[0-9]+:[0-9]+\]}}, s{{\[[0-9]+:[0-9]+\]}}, s[[[K_LO]]:[[K_HI]]]
-
-; SI: s_add_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0x3039
-; SI: s_addc_u32 s{{[0-9]+}}, s{{[0-9]+}}, 0xf237b
define amdgpu_kernel void @scalar_or_literal_multi_use_i64(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
+; GFX6-LABEL: scalar_or_literal_multi_use_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x13
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x1d
+; GFX6-NEXT: s_movk_i32 s8, 0x3039
+; GFX6-NEXT: s_mov_b32 s9, 0xf237b
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
+; GFX6-NEXT: v_mov_b32_e32 v0, s2
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: v_mov_b32_e32 v1, s3
+; GFX6-NEXT: s_add_u32 s0, s0, 0x3039
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_addc_u32 s1, s1, 0xf237b
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: scalar_or_literal_multi_use_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x24
+; GFX8-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x4c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x74
+; GFX8-NEXT: s_movk_i32 s8, 0x3039
+; GFX8-NEXT: s_mov_b32 s9, 0xf237b
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_or_b64 s[2:3], s[2:3], s[8:9]
+; GFX8-NEXT: v_mov_b32_e32 v0, s2
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: v_mov_b32_e32 v1, s3
+; GFX8-NEXT: s_add_u32 s0, s0, 0x3039
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-NEXT: s_addc_u32 s1, s1, 0xf237b
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: scalar_or_literal_multi_use_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 12, @6, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XY, T4.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 6:
+; EG-NEXT: ADDC_UINT * T0.W, KC0[7].Y, literal.x,
+; EG-NEXT: 12345(1.729903e-41), 0(0.000000e+00)
+; EG-NEXT: ADD_INT T0.X, KC0[7].Y, literal.x,
+; EG-NEXT: ADD_INT * T0.W, KC0[7].Z, PV.W,
+; EG-NEXT: 12345(1.729903e-41), 0(0.000000e+00)
+; EG-NEXT: ADD_INT T1.X, PV.W, literal.x,
+; EG-NEXT: MOV * T2.X, literal.y,
+; EG-NEXT: 992123(1.390260e-39), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T3.Y, KC0[5].X, literal.x,
+; EG-NEXT: 992123(1.390260e-39), 0(0.000000e+00)
+; EG-NEXT: OR_INT T3.X, KC0[4].W, literal.x,
+; EG-NEXT: LSHR * T4.X, KC0[2].Y, literal.y,
+; EG-NEXT: 12345(1.729903e-41), 2(2.802597e-45)
%or = or i64 %a, 4261135838621753
store i64 %or, ptr addrspace(1) %out
@@ -91,27 +405,112 @@ define amdgpu_kernel void @scalar_or_literal_multi_use_i64(ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}scalar_or_inline_imm_i64:
-; SI: s_load_dwordx2 s[[[VAL_LO:[0-9]+]]:[[VAL_HI:[0-9]+]]], s{{\[[0-9]+:[0-9]+\]}}, {{0x13|0x4c}}
-; SI-NOT: or_b32
-; SI: s_or_b32 s[[VAL_LO]], s[[VAL_LO]], 63
-; SI-NOT: or_b32
-; SI: v_mov_b32_e32 v[[VLO:[0-9]+]], s[[VAL_LO]]
-; SI-NOT: or_b32
-; SI: v_mov_b32_e32 v[[VHI:[0-9]+]], s[[VAL_HI]]
-; SI-NOT: or_b32
-; SI: buffer_store_dwordx2 v[[[VLO]]:[[VHI]]]
define amdgpu_kernel void @scalar_or_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
+; GFX6-LABEL: scalar_or_inline_imm_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x13
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_or_b32 s4, s4, 63
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: scalar_or_inline_imm_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx2 s[4:5], s[0:1], 0x4c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_or_b32 s4, s4, 63
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: scalar_or_inline_imm_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: MOV * T0.Y, KC0[5].X,
+; EG-NEXT: OR_INT T0.X, KC0[4].W, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 63(8.828180e-44), 2(2.802597e-45)
%or = or i64 %a, 63
store i64 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}scalar_or_inline_imm_multi_use_i64:
-; SI-NOT: or_b32
-; SI: s_or_b32 s{{[0-9]+}}, s{{[0-9]+}}, 63
-; SI-NOT: or_b32
define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {
+; GFX6-LABEL: scalar_or_inline_imm_multi_use_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_or_b32 s4, s6, 63
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s7
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_add_u32 s0, s8, 63
+; GFX6-NEXT: s_addc_u32 s1, s9, 0
+; GFX6-NEXT: s_waitcnt expcnt(0)
+; GFX6-NEXT: v_mov_b32_e32 v0, s0
+; GFX6-NEXT: v_mov_b32_e32 v1, s1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: scalar_or_inline_imm_multi_use_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX8-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s0, s4
+; GFX8-NEXT: s_or_b32 s4, s6, 63
+; GFX8-NEXT: s_mov_b32 s1, s5
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s7
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-NEXT: s_add_u32 s0, s8, 63
+; GFX8-NEXT: s_addc_u32 s1, s9, 0
+; GFX8-NEXT: v_mov_b32_e32 v0, s0
+; GFX8-NEXT: v_mov_b32_e32 v1, s1
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: scalar_or_inline_imm_multi_use_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 9, @6, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T3.XY, T4.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T2.X, 0
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T2.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 6:
+; EG-NEXT: ADD_INT T0.X, KC0[3].Y, literal.x,
+; EG-NEXT: ADDC_UINT * T0.W, KC0[3].Y, literal.x,
+; EG-NEXT: 63(8.828180e-44), 0(0.000000e+00)
+; EG-NEXT: ADD_INT T1.X, KC0[3].Z, PV.W,
+; EG-NEXT: MOV * T2.X, literal.x,
+; EG-NEXT: 0(0.000000e+00), 0(0.000000e+00)
+; EG-NEXT: MOV * T3.Y, KC0[3].X,
+; EG-NEXT: OR_INT T3.X, KC0[2].W, literal.x,
+; EG-NEXT: LSHR * T4.X, KC0[2].Y, literal.y,
+; EG-NEXT: 63(8.828180e-44), 2(2.802597e-45)
%or = or i64 %a, 63
store i64 %or, ptr addrspace(1) %out
%foo = add i64 %b, 63
@@ -119,51 +518,281 @@ define amdgpu_kernel void @scalar_or_inline_imm_multi_use_i64(ptr addrspace(1) %
ret void
}
-; FUNC-LABEL: {{^}}scalar_or_neg_inline_imm_i64:
-; SI-DAG: s_load_dword [[VAL:s[0-9]+]]
-; SI-DAG: s_or_b32 [[VAL]], [[VAL]], -8
-; SI-DAG: v_mov_b32_e32 v[[V_HI:[0-9]+]], -1{{$}}
-; SI-DAG: v_mov_b32_e32 v[[V_LO:[0-9]+]], [[VAL]]
-; SI: buffer_store_dwordx2 v[[[V_LO]]:[[V_HI]]]
define amdgpu_kernel void @scalar_or_neg_inline_imm_i64(ptr addrspace(1) %out, [8 x i32], i64 %a) {
+; GFX6-LABEL: scalar_or_neg_inline_imm_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s4, s[0:1], 0x13
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: v_mov_b32_e32 v1, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_or_b32 s4, s4, -8
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: scalar_or_neg_inline_imm_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dword s4, s[0:1], 0x4c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: v_mov_b32_e32 v1, -1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_or_b32 s4, s4, -8
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: scalar_or_neg_inline_imm_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 4, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: OR_INT T0.X, KC0[4].W, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: -8(nan), 2(2.802597e-45)
+; EG-NEXT: MOV * T0.Y, literal.x,
+; EG-NEXT: -1(nan), 0(0.000000e+00)
%or = or i64 %a, -8
store i64 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}vector_or_literal_i32:
-; SI: v_or_b32_e32 v{{[0-9]+}}, 0xffff, v{{[0-9]+}}
define amdgpu_kernel void @vector_or_literal_i32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; GFX6-LABEL: vector_or_literal_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v0, 0xffff, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: vector_or_literal_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: s_mov_b32 s10, s6
+; GFX8-NEXT: s_mov_b32 s11, s7
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s2
+; GFX8-NEXT: s_mov_b32 s9, s3
+; GFX8-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s4, s0
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, 0xffff, v0
+; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: vector_or_literal_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: OR_INT T0.X, T0.X, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 65535(9.183409e-41), 2(2.802597e-45)
%loada = load i32, ptr addrspace(1) %a, align 4
%or = or i32 %loada, 65535
store i32 %or, ptr addrspace(1) %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}vector_or_inline_immediate_i32:
-; SI: v_or_b32_e32 v{{[0-9]+}}, 4, v{{[0-9]+}}
define amdgpu_kernel void @vector_or_inline_immediate_i32(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; GFX6-LABEL: vector_or_inline_immediate_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v0, 4, v0
+; GFX6-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: vector_or_inline_immediate_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: s_mov_b32 s10, s6
+; GFX8-NEXT: s_mov_b32 s11, s7
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s2
+; GFX8-NEXT: s_mov_b32 s9, s3
+; GFX8-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s4, s0
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, 4, v0
+; GFX8-NEXT: buffer_store_dword v0, off, s[4:7], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: vector_or_inline_immediate_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: OR_INT T0.X, T0.X, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 4(5.605194e-45), 2(2.802597e-45)
%loada = load i32, ptr addrspace(1) %a, align 4
%or = or i32 %loada, 4
store i32 %or, ptr addrspace(1) %out, align 4
ret void
}
-; FUNC-LABEL: {{^}}scalar_or_i64:
-; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[2].W, KC0[3].Y
-; EG-DAG: OR_INT * T{{[0-9]\.[XYZW]}}, KC0[3].X, KC0[3].Z
-
-; SI: s_or_b64
define amdgpu_kernel void @scalar_or_i64(ptr addrspace(1) %out, i64 %a, i64 %b) {
+; GFX6-LABEL: scalar_or_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9]
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: v_mov_b32_e32 v1, s5
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: scalar_or_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX8-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s0, s4
+; GFX8-NEXT: s_mov_b32 s1, s5
+; GFX8-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9]
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: v_mov_b32_e32 v1, s5
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: scalar_or_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: OR_INT * T0.Y, KC0[3].X, KC0[3].Z,
+; EG-NEXT: OR_INT * T0.X, KC0[2].W, KC0[3].Y,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%or = or i64 %a, %b
store i64 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}vector_or_i64:
-; SI: v_or_b32_e32 v{{[0-9]}}
-; SI: v_or_b32_e32 v{{[0-9]}}
define amdgpu_kernel void @vector_or_i64(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; GFX6-LABEL: vector_or_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_mov_b32 s10, s2
+; GFX6-NEXT: s_mov_b32 s11, s3
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s12, s6
+; GFX6-NEXT: s_mov_b32 s13, s7
+; GFX6-NEXT: s_mov_b32 s14, s2
+; GFX6-NEXT: s_mov_b32 s15, s3
+; GFX6-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; GFX6-NEXT: buffer_load_dwordx2 v[2:3], off, s[12:15], 0
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX6-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: vector_or_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX8-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_mov_b32 s10, s2
+; GFX8-NEXT: s_mov_b32 s11, s3
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s12, s6
+; GFX8-NEXT: s_mov_b32 s13, s7
+; GFX8-NEXT: s_mov_b32 s14, s2
+; GFX8-NEXT: s_mov_b32 s15, s3
+; GFX8-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; GFX8-NEXT: buffer_load_dwordx2 v[2:3], off, s[12:15], 0
+; GFX8-NEXT: s_mov_b32 s0, s4
+; GFX8-NEXT: s_mov_b32 s1, s5
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, v2, v0
+; GFX8-NEXT: v_or_b32_e32 v1, v3, v1
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: vector_or_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 1, @10, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 1 @6
+; EG-NEXT: ALU 3, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T1.XY, T1.X, 0, #1
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 10:
+; EG-NEXT: MOV T0.X, KC0[2].Z,
+; EG-NEXT: MOV * T1.X, KC0[2].W,
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: OR_INT * T0.Y, T0.Y, T1.Y,
+; EG-NEXT: OR_INT T0.X, T0.X, T1.X,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%loada = load i64, ptr addrspace(1) %a, align 8
%loadb = load i64, ptr addrspace(1) %b, align 8
%or = or i64 %loada, %loadb
@@ -171,22 +800,127 @@ define amdgpu_kernel void @vector_or_i64(ptr addrspace(1) %out, ptr addrspace(1)
ret void
}
-; FUNC-LABEL: {{^}}scalar_vector_or_i64:
-; SI: v_or_b32_e32 v{{[0-9]}}
-; SI: v_or_b32_e32 v{{[0-9]}}
define amdgpu_kernel void @scalar_vector_or_i64(ptr addrspace(1) %out, ptr addrspace(1) %a, i64 %b) {
+; GFX6-LABEL: scalar_vector_or_i64:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_mov_b32 s10, s2
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s6
+; GFX6-NEXT: s_mov_b32 s9, s7
+; GFX6-NEXT: s_mov_b32 s11, s3
+; GFX6-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s0, s4
+; GFX6-NEXT: s_mov_b32 s1, s5
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v0, s12, v0
+; GFX6-NEXT: v_or_b32_e32 v1, s13, v1
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: scalar_vector_or_i64:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX8-NEXT: s_load_dwordx2 s[12:13], s[0:1], 0x34
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_mov_b32 s10, s2
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s6
+; GFX8-NEXT: s_mov_b32 s9, s7
+; GFX8-NEXT: s_mov_b32 s11, s3
+; GFX8-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s0, s4
+; GFX8-NEXT: s_mov_b32 s1, s5
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, s12, v0
+; GFX8-NEXT: v_or_b32_e32 v1, s13, v1
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: scalar_vector_or_i64:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 3, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: OR_INT * T0.Y, T0.Y, KC0[3].X,
+; EG-NEXT: OR_INT T0.X, T0.X, KC0[2].W,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%loada = load i64, ptr addrspace(1) %a
%or = or i64 %loada, %b
store i64 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}vector_or_i64_loadimm:
-; SI-DAG: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xdf77987f, v[[LO_VREG]]
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0x146f, v[[HI_VREG]]
-; SI: s_endpgm
define amdgpu_kernel void @vector_or_i64_loadimm(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; GFX6-LABEL: vector_or_i64_loadimm:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v1, 0x146f, v1
+; GFX6-NEXT: v_or_b32_e32 v0, 0xdf77987f, v0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: vector_or_i64_loadimm:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: s_mov_b32 s10, s6
+; GFX8-NEXT: s_mov_b32 s11, s7
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s2
+; GFX8-NEXT: s_mov_b32 s9, s3
+; GFX8-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s4, s0
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v1, 0x146f, v1
+; GFX8-NEXT: v_or_b32_e32 v0, 0xdf77987f, v0
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: vector_or_i64_loadimm:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: OR_INT * T0.Y, T0.Y, literal.x,
+; EG-NEXT: 5231(7.330192e-42), 0(0.000000e+00)
+; EG-NEXT: OR_INT T0.X, T0.X, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: -545810305(-1.784115e+19), 2(2.802597e-45)
%loada = load i64, ptr addrspace(1) %a, align 8
%or = or i64 %loada, 22470723082367
store i64 %or, ptr addrspace(1) %out
@@ -194,63 +928,312 @@ define amdgpu_kernel void @vector_or_i64_loadimm(ptr addrspace(1) %out, ptr addr
}
; FIXME: The or 0 should really be removed.
-; FUNC-LABEL: {{^}}vector_or_i64_imm:
-; SI: buffer_load_dwordx2 v[[[LO_VREG:[0-9]+]]:[[HI_VREG:[0-9]+]]],
-; SI: v_or_b32_e32 v[[LO_RESULT:[0-9]+]], 8, v[[LO_VREG]]
-; SI-NOT: v_or_b32_e32 {{v[0-9]+}}, 0
-; SI: buffer_store_dwordx2 v[[[LO_RESULT]]:[[HI_VREG]]]
-; SI: s_endpgm
define amdgpu_kernel void @vector_or_i64_imm(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; GFX6-LABEL: vector_or_i64_imm:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v0, 8, v0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: vector_or_i64_imm:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: s_mov_b32 s10, s6
+; GFX8-NEXT: s_mov_b32 s11, s7
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s2
+; GFX8-NEXT: s_mov_b32 s9, s3
+; GFX8-NEXT: buffer_load_dwordx2 v[0:1], off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s4, s0
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, 8, v0
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: vector_or_i64_imm:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 2, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_64 T0.XY, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: OR_INT T0.X, T0.X, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: 8(1.121039e-44), 2(2.802597e-45)
%loada = load i64, ptr addrspace(1) %a, align 8
%or = or i64 %loada, 8
store i64 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}vector_or_i64_neg_inline_imm:
-; SI-DAG: buffer_load_dword v[[LO_VREG:[0-9]+]]
-; SI-DAG: v_or_b32_e32 v[[RES_LO:[0-9]+]], -8, v[[LO_VREG]]
-; SI-DAG: v_mov_b32_e32 v[[RES_HI:[0-9]+]], -1{{$}}
-; SI: buffer_store_dwordx2 v[[[RES_LO]]:[[RES_HI]]]
-; SI: s_endpgm
define amdgpu_kernel void @vector_or_i64_neg_inline_imm(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; GFX6-LABEL: vector_or_i64_neg_inline_imm:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: v_mov_b32_e32 v1, -1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v0, -8, v0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: vector_or_i64_neg_inline_imm:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: s_mov_b32 s10, s6
+; GFX8-NEXT: s_mov_b32 s11, s7
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s2
+; GFX8-NEXT: s_mov_b32 s9, s3
+; GFX8-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s4, s0
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, -1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, -8, v0
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: vector_or_i64_neg_inline_imm:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: OR_INT T0.X, T0.X, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: -8(nan), 2(2.802597e-45)
+; EG-NEXT: MOV * T0.Y, literal.x,
+; EG-NEXT: -1(nan), 0(0.000000e+00)
%loada = load i64, ptr addrspace(1) %a, align 8
%or = or i64 %loada, -8
store i64 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}vector_or_i64_neg_literal:
-; SI-DAG: buffer_load_dword v[[LO_VREG:[0-9]+]]
-; SI-DAG: v_mov_b32_e32 v{{[0-9]+}}, -1{{$}}
-; SI-DAG: v_or_b32_e32 {{v[0-9]+}}, 0xffffff38, v[[LO_VREG]]
-; SI: buffer_store_dwordx2
-; SI: s_endpgm
define amdgpu_kernel void @vector_or_i64_neg_literal(ptr addrspace(1) %out, ptr addrspace(1) %a, ptr addrspace(1) %b) {
+; GFX6-LABEL: vector_or_i64_neg_literal:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s7, 0xf000
+; GFX6-NEXT: s_mov_b32 s6, -1
+; GFX6-NEXT: s_mov_b32 s10, s6
+; GFX6-NEXT: s_mov_b32 s11, s7
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s8, s2
+; GFX6-NEXT: s_mov_b32 s9, s3
+; GFX6-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX6-NEXT: s_mov_b32 s4, s0
+; GFX6-NEXT: s_mov_b32 s5, s1
+; GFX6-NEXT: v_mov_b32_e32 v1, -1
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_or_b32_e32 v0, 0xffffff38, v0
+; GFX6-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: vector_or_i64_neg_literal:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s7, 0xf000
+; GFX8-NEXT: s_mov_b32 s6, -1
+; GFX8-NEXT: s_mov_b32 s10, s6
+; GFX8-NEXT: s_mov_b32 s11, s7
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s8, s2
+; GFX8-NEXT: s_mov_b32 s9, s3
+; GFX8-NEXT: buffer_load_dword v0, off, s[8:11], 0
+; GFX8-NEXT: s_mov_b32 s4, s0
+; GFX8-NEXT: s_mov_b32 s5, s1
+; GFX8-NEXT: v_mov_b32_e32 v1, -1
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_or_b32_e32 v0, 0xffffff38, v0
+; GFX8-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: vector_or_i64_neg_literal:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @8, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @6
+; EG-NEXT: ALU 4, @9, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 6:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: ALU clause starting at 8:
+; EG-NEXT: MOV * T0.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 9:
+; EG-NEXT: OR_INT T0.X, T0.X, literal.x,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.y,
+; EG-NEXT: -200(nan), 2(2.802597e-45)
+; EG-NEXT: MOV * T0.Y, literal.x,
+; EG-NEXT: -1(nan), 0(0.000000e+00)
%loada = load i64, ptr addrspace(1) %a, align 8
%or = or i64 %loada, -200
store i64 %or, ptr addrspace(1) %out
ret void
}
-; FUNC-LABEL: {{^}}trunc_i64_or_to_i32:
-; SI: s_load_dword s[[SREG0:[0-9]+]]
-; SI: s_load_dword s[[SREG1:[0-9]+]]
-; SI: s_or_b32 s[[SRESULT:[0-9]+]], s[[SREG1]], s[[SREG0]]
-; SI: v_mov_b32_e32 [[VRESULT:v[0-9]+]], s[[SRESULT]]
-; SI: buffer_store_dword [[VRESULT]],
define amdgpu_kernel void @trunc_i64_or_to_i32(ptr addrspace(1) %out, [8 x i32], i64 %a, [8 x i32], i64 %b) {
+; GFX6-LABEL: trunc_i64_or_to_i32:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dword s4, s[0:1], 0x13
+; GFX6-NEXT: s_load_dword s5, s[0:1], 0x1d
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_or_b32 s4, s5, s4
+; GFX6-NEXT: v_mov_b32_e32 v0, s4
+; GFX6-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: trunc_i64_or_to_i32:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dword s4, s[0:1], 0x4c
+; GFX8-NEXT: s_load_dword s5, s[0:1], 0x74
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_or_b32 s4, s5, s4
+; GFX8-NEXT: v_mov_b32_e32 v0, s4
+; GFX8-NEXT: buffer_store_dword v0, off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: trunc_i64_or_to_i32:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
+; EG-NEXT: OR_INT * T1.X, KC0[7].Y, KC0[4].W,
%add = or i64 %b, %a
%trunc = trunc i64 %add to i32
store i32 %trunc, ptr addrspace(1) %out, align 8
ret void
}
-; FUNC-LABEL: {{^}}or_i1:
-; EG: OR_INT * {{\** *}}T{{[0-9]+\.[XYZW], PS, PV\.[XYZW]}}
-
-; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], vcc
define amdgpu_kernel void @or_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) {
+; GFX6-LABEL: or_i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x9
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0xd
+; GFX6-NEXT: s_mov_b32 s11, 0xf000
+; GFX6-NEXT: s_mov_b32 s10, -1
+; GFX6-NEXT: s_mov_b32 s2, s10
+; GFX6-NEXT: s_mov_b32 s3, s11
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_mov_b32 s12, s6
+; GFX6-NEXT: s_mov_b32 s13, s7
+; GFX6-NEXT: s_mov_b32 s14, s10
+; GFX6-NEXT: s_mov_b32 s15, s11
+; GFX6-NEXT: buffer_load_dword v0, off, s[0:3], 0
+; GFX6-NEXT: buffer_load_dword v1, off, s[12:15], 0
+; GFX6-NEXT: s_mov_b32 s8, s4
+; GFX6-NEXT: s_mov_b32 s9, s5
+; GFX6-NEXT: s_waitcnt vmcnt(1)
+; GFX6-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
+; GFX6-NEXT: s_waitcnt vmcnt(0)
+; GFX6-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
+; GFX6-NEXT: s_or_b64 s[0:1], s[0:1], vcc
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; GFX6-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: or_i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
+; GFX8-NEXT: s_mov_b32 s11, 0xf000
+; GFX8-NEXT: s_mov_b32 s10, -1
+; GFX8-NEXT: s_mov_b32 s2, s10
+; GFX8-NEXT: s_mov_b32 s3, s11
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_mov_b32 s12, s6
+; GFX8-NEXT: s_mov_b32 s13, s7
+; GFX8-NEXT: s_mov_b32 s14, s10
+; GFX8-NEXT: s_mov_b32 s15, s11
+; GFX8-NEXT: buffer_load_dword v0, off, s[0:3], 0
+; GFX8-NEXT: buffer_load_dword v1, off, s[12:15], 0
+; GFX8-NEXT: s_mov_b32 s8, s4
+; GFX8-NEXT: s_mov_b32 s9, s5
+; GFX8-NEXT: s_waitcnt vmcnt(1)
+; GFX8-NEXT: v_cmp_le_f32_e32 vcc, 0, v0
+; GFX8-NEXT: s_waitcnt vmcnt(0)
+; GFX8-NEXT: v_cmp_le_f32_e64 s[0:1], 0, v1
+; GFX8-NEXT: s_or_b64 s[0:1], s[0:1], vcc
+; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[0:1]
+; GFX8-NEXT: buffer_store_dword v0, off, s[8:11], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: or_i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @8
+; EG-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]
+; EG-NEXT: TEX 0 @10
+; EG-NEXT: ALU 5, @14, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: Fetch clause starting at 8:
+; EG-NEXT: VTX_READ_32 T0.X, T0.X, 0, #1
+; EG-NEXT: Fetch clause starting at 10:
+; EG-NEXT: VTX_READ_32 T1.X, T1.X, 0, #1
+; EG-NEXT: ALU clause starting at 12:
+; EG-NEXT: MOV * T0.X, KC0[2].W,
+; EG-NEXT: ALU clause starting at 13:
+; EG-NEXT: MOV * T1.X, KC0[2].Z,
+; EG-NEXT: ALU clause starting at 14:
+; EG-NEXT: SETGE_DX10 T0.W, T0.X, 0.0,
+; EG-NEXT: SETGE_DX10 * T1.W, T1.X, 0.0,
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: AND_INT T0.X, PV.W, 1,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%a = load float, ptr addrspace(1) %in0
%b = load float, ptr addrspace(1) %in1
%acmp = fcmp oge float %a, 0.000000e+00
@@ -261,16 +1244,65 @@ define amdgpu_kernel void @or_i1(ptr addrspace(1) %out, ptr addrspace(1) %in0, p
ret void
}
-; FUNC-LABEL: {{^}}s_or_i1:
-; SI: s_cmp_eq_u32
-; SI: s_cselect_b64 [[C1:[^,]+]], -1, 0
-; SI: s_cmp_eq_u32
-; SI: s_cselect_b64 [[C2:[^,]+]], -1, 0
-; SI: s_or_b64 s[{{[0-9]+:[0-9]+}}], [[C1]], [[C2]]
define amdgpu_kernel void @s_or_i1(ptr addrspace(1) %out, i32 %a, i32 %b, i32 %c, i32 %d) {
+; GFX6-LABEL: s_or_i1:
+; GFX6: ; %bb.0:
+; GFX6-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0xb
+; GFX6-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x9
+; GFX6-NEXT: s_mov_b32 s3, 0xf000
+; GFX6-NEXT: s_mov_b32 s2, -1
+; GFX6-NEXT: s_waitcnt lgkmcnt(0)
+; GFX6-NEXT: s_cmp_eq_u32 s4, s5
+; GFX6-NEXT: s_cselect_b64 s[4:5], -1, 0
+; GFX6-NEXT: s_cmp_eq_u32 s6, s7
+; GFX6-NEXT: s_cselect_b64 s[6:7], -1, 0
+; GFX6-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; GFX6-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX6-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; GFX6-NEXT: s_endpgm
+;
+; GFX8-LABEL: s_or_i1:
+; GFX8: ; %bb.0:
+; GFX8-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x2c
+; GFX8-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
+; GFX8-NEXT: s_mov_b32 s3, 0xf000
+; GFX8-NEXT: s_mov_b32 s2, -1
+; GFX8-NEXT: s_waitcnt lgkmcnt(0)
+; GFX8-NEXT: s_cmp_eq_u32 s4, s5
+; GFX8-NEXT: s_cselect_b64 s[4:5], -1, 0
+; GFX8-NEXT: s_cmp_eq_u32 s6, s7
+; GFX8-NEXT: s_cselect_b64 s[6:7], -1, 0
+; GFX8-NEXT: s_or_b64 s[4:5], s[4:5], s[6:7]
+; GFX8-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
+; GFX8-NEXT: buffer_store_byte v0, off, s[0:3], 0
+; GFX8-NEXT: s_endpgm
+;
+; EG-LABEL: s_or_i1:
+; EG: ; %bb.0:
+; EG-NEXT: ALU 14, @4, KC0[CB0:0-32], KC1[]
+; EG-NEXT: MEM_RAT MSKOR T0.XW, T1.X
+; EG-NEXT: CF_END
+; EG-NEXT: PAD
+; EG-NEXT: ALU clause starting at 4:
+; EG-NEXT: SETE_INT T0.W, KC0[3].X, KC0[3].Y,
+; EG-NEXT: SETE_INT * T1.W, KC0[2].Z, KC0[2].W,
+; EG-NEXT: AND_INT T2.W, KC0[2].Y, literal.x,
+; EG-NEXT: OR_INT * T0.W, PS, PV.W,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: AND_INT T0.W, PS, 1,
+; EG-NEXT: LSHL * T1.W, PV.W, literal.x,
+; EG-NEXT: 3(4.203895e-45), 0(0.000000e+00)
+; EG-NEXT: LSHL T0.X, PV.W, PS,
+; EG-NEXT: LSHL * T0.W, literal.x, PS,
+; EG-NEXT: 255(3.573311e-43), 0(0.000000e+00)
+; EG-NEXT: MOV T0.Y, 0.0,
+; EG-NEXT: MOV * T0.Z, 0.0,
+; EG-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
+; EG-NEXT: 2(2.802597e-45), 0(0.000000e+00)
%cmp0 = icmp eq i32 %a, %b
%cmp1 = icmp eq i32 %c, %d
%or = or i1 %cmp0, %cmp1
store i1 %or, ptr addrspace(1) %out
ret void
}
+
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