[llvm] 3a0a25f - [RISCV] Support i32 clmul* intrinsics on RV64.
Craig Topper via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 14 11:20:41 PDT 2023
Author: Craig Topper
Date: 2023-07-14T11:20:03-07:00
New Revision: 3a0a25f9b600b3f18810c4287f0f2e4e48cca68e
URL: https://github.com/llvm/llvm-project/commit/3a0a25f9b600b3f18810c4287f0f2e4e48cca68e
DIFF: https://github.com/llvm/llvm-project/commit/3a0a25f9b600b3f18810c4287f0f2e4e48cca68e.diff
LOG: [RISCV] Support i32 clmul* intrinsics on RV64.
We can use an i64 clmul to emulate i32 clmul.
For clmulh and clmulr we need to zero extend the 32 bit input
to 64 bits then extract either bits [63:32] or [62:31].
Unfortunately, without Zba we need to use 2 shifts for the
zero extends. These can be optimized out later if the producing
instruction already zeroed the upper bits or if we can use lwu.
There are alternative sequences we can use for clmulh/clmulr
when the zero extend isn't free, but those are best handled by
a DAG combine to give the best opportunity for removing the extend.
This allows us to implement i32 clmul C intrinsics proposed in
https://github.com/riscv-non-isa/riscv-c-api-doc/pull/44.
Reviewed By: asb
Differential Revision: https://reviews.llvm.org/D154729
Added:
Modified:
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVISelLowering.h
llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
Removed:
################################################################################
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
index 45fcfdaca88867..4388bbf8ae8d8e 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7018,6 +7018,15 @@ SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
IntNo == Intrinsic::riscv_zip ? RISCVISD::ZIP : RISCVISD::UNZIP;
return DAG.getNode(Opc, DL, XLenVT, Op.getOperand(1));
}
+ case Intrinsic::riscv_clmul:
+ return DAG.getNode(RISCVISD::CLMUL, DL, XLenVT, Op.getOperand(1),
+ Op.getOperand(2));
+ case Intrinsic::riscv_clmulh:
+ return DAG.getNode(RISCVISD::CLMULH, DL, XLenVT, Op.getOperand(1),
+ Op.getOperand(2));
+ case Intrinsic::riscv_clmulr:
+ return DAG.getNode(RISCVISD::CLMULR, DL, XLenVT, Op.getOperand(1),
+ Op.getOperand(2));
case Intrinsic::experimental_get_vector_length:
return lowerGetVectorLength(Op.getNode(), DAG, Subtarget);
case Intrinsic::riscv_vmv_x_s:
@@ -9891,6 +9900,34 @@ void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
return;
}
+ case Intrinsic::riscv_clmul: {
+ if (!Subtarget.is64Bit() || N->getValueType(0) != MVT::i32)
+ return;
+
+ SDValue NewOp0 =
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(1));
+ SDValue NewOp1 =
+ DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, N->getOperand(2));
+ SDValue Res = DAG.getNode(RISCVISD::CLMUL, DL, MVT::i64, NewOp0, NewOp1);
+ Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+ return;
+ }
+ case Intrinsic::riscv_clmulh:
+ case Intrinsic::riscv_clmulr: {
+ if (!Subtarget.is64Bit() || N->getValueType(0) != MVT::i32)
+ return;
+
+ SDValue NewOp0 =
+ DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(1));
+ SDValue NewOp1 =
+ DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, N->getOperand(2));
+ SDValue Res = DAG.getNode(RISCVISD::CLMUL, DL, MVT::i64, NewOp0, NewOp1);
+ unsigned ShAmt = IntNo == Intrinsic::riscv_clmulh ? 32 : 31;
+ Res = DAG.getNode(ISD::SRL, DL, MVT::i64, Res,
+ DAG.getConstant(ShAmt, DL, MVT::i64));
+ Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
+ return;
+ }
case Intrinsic::riscv_vmv_x_s: {
EVT VT = N->getValueType(0);
MVT XLenVT = Subtarget.getXLenVT();
@@ -15873,6 +15910,9 @@ const char *RISCVTargetLowering::getTargetNodeName(unsigned Opcode) const {
NODE_NAME_CASE(ORC_B)
NODE_NAME_CASE(ZIP)
NODE_NAME_CASE(UNZIP)
+ NODE_NAME_CASE(CLMUL)
+ NODE_NAME_CASE(CLMULH)
+ NODE_NAME_CASE(CLMULR)
NODE_NAME_CASE(TH_LWD)
NODE_NAME_CASE(TH_LWUD)
NODE_NAME_CASE(TH_LDD)
diff --git a/llvm/lib/Target/RISCV/RISCVISelLowering.h b/llvm/lib/Target/RISCV/RISCVISelLowering.h
index e016c1f456e7f4..03bc1d8471558b 100644
--- a/llvm/lib/Target/RISCV/RISCVISelLowering.h
+++ b/llvm/lib/Target/RISCV/RISCVISelLowering.h
@@ -128,6 +128,10 @@ enum NodeType : unsigned {
ORC_B,
ZIP,
UNZIP,
+
+ // Scalar cryptography
+ CLMUL, CLMULH, CLMULR,
+
// Vector Extension
// VMV_V_V_VL matches the semantics of vmv.v.v but includes an extra operand
// for the VL value to be used for the operation. The first operand is
diff --git a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
index 55731ea908f48f..b709dc67ce84bd 100644
--- a/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
+++ b/llvm/lib/Target/RISCV/RISCVInstrInfoZb.td
@@ -38,6 +38,9 @@ def riscv_orc_b : SDNode<"RISCVISD::ORC_B", SDTIntUnaryOp>;
def riscv_zip : SDNode<"RISCVISD::ZIP", SDTIntUnaryOp>;
def riscv_unzip : SDNode<"RISCVISD::UNZIP", SDTIntUnaryOp>;
def riscv_absw : SDNode<"RISCVISD::ABSW", SDTIntUnaryOp>;
+def riscv_clmul : SDNode<"RISCVISD::CLMUL", SDTIntBinOp>;
+def riscv_clmulh : SDNode<"RISCVISD::CLMULH", SDTIntBinOp>;
+def riscv_clmulr : SDNode<"RISCVISD::CLMULR", SDTIntBinOp>;
def UImmLog2XLenHalfAsmOperand : AsmOperandClass {
let Name = "UImmLog2XLenHalf";
@@ -790,12 +793,12 @@ def : Pat<(i64 (mul (and_oneuse GPR:$r, 0xFFFFFFFF), C9LeftShiftUW:$i)),
} // Predicates = [HasStdExtZba, IsRV64]
let Predicates = [HasStdExtZbcOrZbkc] in {
-def : PatGprGpr<int_riscv_clmul, CLMUL>;
-def : PatGprGpr<int_riscv_clmulh, CLMULH>;
+def : PatGprGpr<riscv_clmul, CLMUL>;
+def : PatGprGpr<riscv_clmulh, CLMULH>;
} // Predicates = [HasStdExtZbcOrZbkc]
let Predicates = [HasStdExtZbc] in
-def : PatGprGpr<int_riscv_clmulr, CLMULR>;
+def : PatGprGpr<riscv_clmulr, CLMULR>;
let Predicates = [HasStdExtZbkx] in {
def : PatGprGpr<int_riscv_xperm4, XPERM4>;
diff --git a/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
index cb5cc048b98977..368d9fb2f7e02e 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbc-intrinsic.ll
@@ -12,3 +12,20 @@ define i64 @clmul64r(i64 %a, i64 %b) nounwind {
%tmp = call i64 @llvm.riscv.clmulr.i64(i64 %a, i64 %b)
ret i64 %tmp
}
+
+declare i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
+
+define signext i32 @clmul32r(i32 signext %a, i32 signext %b) nounwind {
+; RV64ZBC-LABEL: clmul32r:
+; RV64ZBC: # %bb.0:
+; RV64ZBC-NEXT: slli a1, a1, 32
+; RV64ZBC-NEXT: srli a1, a1, 32
+; RV64ZBC-NEXT: slli a0, a0, 32
+; RV64ZBC-NEXT: srli a0, a0, 32
+; RV64ZBC-NEXT: clmul a0, a0, a1
+; RV64ZBC-NEXT: srli a0, a0, 31
+; RV64ZBC-NEXT: sext.w a0, a0
+; RV64ZBC-NEXT: ret
+ %tmp = call i32 @llvm.riscv.clmulr.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
diff --git a/llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll b/llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
index faa734f989ef2d..a7ba0412bb2750 100644
--- a/llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
+++ b/llvm/test/CodeGen/RISCV/rv64zbc-zbkc-intrinsic.ll
@@ -26,3 +26,31 @@ define i64 @clmul64h(i64 %a, i64 %b) nounwind {
ret i64 %tmp
}
+declare i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+
+define signext i32 @clmul32(i32 signext %a, i32 signext %b) nounwind {
+; RV64ZBC-ZBKC-LABEL: clmul32:
+; RV64ZBC-ZBKC: # %bb.0:
+; RV64ZBC-ZBKC-NEXT: clmul a0, a0, a1
+; RV64ZBC-ZBKC-NEXT: sext.w a0, a0
+; RV64ZBC-ZBKC-NEXT: ret
+ %tmp = call i32 @llvm.riscv.clmul.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
+declare i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+
+define signext i32 @clmul32h(i32 signext %a, i32 signext %b) nounwind {
+; RV64ZBC-ZBKC-LABEL: clmul32h:
+; RV64ZBC-ZBKC: # %bb.0:
+; RV64ZBC-ZBKC-NEXT: slli a1, a1, 32
+; RV64ZBC-ZBKC-NEXT: srli a1, a1, 32
+; RV64ZBC-ZBKC-NEXT: slli a0, a0, 32
+; RV64ZBC-ZBKC-NEXT: srli a0, a0, 32
+; RV64ZBC-ZBKC-NEXT: clmul a0, a0, a1
+; RV64ZBC-ZBKC-NEXT: srai a0, a0, 32
+; RV64ZBC-ZBKC-NEXT: ret
+ %tmp = call i32 @llvm.riscv.clmulh.i32(i32 %a, i32 %b)
+ ret i32 %tmp
+}
+
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