[PATCH] D155288: [RISCV] Add a new select combine for when the condition is a setcc that will be inverted

[Mikhail Gudim via Phabricator via llvm-commits]

mgudim added inline comments.


================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:12300
+  ISD::CondCode CCVal = cast<CondCodeSDNode>(V.getOperand(2))->get();
+  return V.getOperand(0).getValueType().isInteger() &&
+         (CCVal == ISD::SETGE || CCVal == ISD::SETLE || CCVal == ISD::SETUGE ||
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mgudim wrote:
> what about floating-point?
nvm, I understand why its limited to integers only.


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155288/new/

https://reviews.llvm.org/D155288