[llvm] 4c1e36f - [PowerPC] Add DFP test instruction definitions and MC tests
Kamau Bridgeman via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 14 11:00:42 PDT 2023
Author: Kamau Bridgeman
Date: 2023-07-14T13:00:37-05:00
New Revision: 4c1e36fa642fe008662719be35d704649996d59b
URL: https://github.com/llvm/llvm-project/commit/4c1e36fa642fe008662719be35d704649996d59b
DIFF: https://github.com/llvm/llvm-project/commit/4c1e36fa642fe008662719be35d704649996d59b.diff
LOG: [PowerPC] Add DFP test instruction definitions and MC tests
Adding the td definitions, and their associated assembly and disassembly
test cases for the decimal floating point test instructions defined in
section 5.6.3 of ISA 3.1
Reviewed By: lei, amyk
Differential Revision: https://reviews.llvm.org/D154606
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrDFP.td
llvm/lib/Target/PowerPC/PPCInstrFormats.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrDFP.td b/llvm/lib/Target/PowerPC/PPCInstrDFP.td
index 6ce6cb39ea08d6..f4908e325e13c1 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrDFP.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrDFP.td
@@ -152,4 +152,42 @@ defm DSCRI: Z22Form_FRTA5_SH6r<59, 98, (outs f8rc:$FRT),
defm DSCRIQ: Z22Form_FRTA5_SH6r<63, 98, (outs fpairrc:$FRT),
(ins fpairrc:$FRA, u6imm:$SH),
"dscriq", "$FRT, $FRA, $SH", []>;
+
+// 5.6.3 DFP Test Instructions
+def DTSTDC : Z22Form_BF3_FRA5_DCM6<59, 194, (outs crrc:$BF),
+ (ins f8rc:$FRA, u6imm:$DCM),
+ "dtstdc $BF, $FRA, $DCM", IIC_FPCompare, []>;
+
+def DTSTDCQ : Z22Form_BF3_FRA5_DCM6<63, 194, (outs crrc:$BF),
+ (ins fpairrc:$FRA, u6imm:$DCM),
+ "dtstdcq $BF, $FRA, $DCM", IIC_FPCompare, []>;
+
+def DTSTDG : Z22Form_BF3_FRA5_DCM6<59, 226, (outs crrc:$BF),
+ (ins f8rc:$FRA, u6imm:$DCM),
+ "dtstdg $BF, $FRA, $DCM", IIC_FPCompare, []>;
+
+def DTSTDGQ : Z22Form_BF3_FRA5_DCM6<63, 226, (outs crrc:$BF),
+ (ins fpairrc:$FRA, u6imm:$DCM),
+ "dtstdgq $BF, $FRA, $DCM", IIC_FPCompare, []>;
+
+def DTSTEX : XForm_17<59, 162, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
+ "dtstex $BF, $RA, $RB", IIC_FPCompare>;
+
+def DTSTEXQ : XForm_17<63, 162, (outs crrc:$BF), (ins fpairrc:$RA, fpairrc:$RB),
+ "dtstexq $BF, $RA, $RB", IIC_FPCompare>;
+
+def DTSTSF : XForm_17<59, 674, (outs crrc:$BF), (ins f8rc:$RA, f8rc:$RB),
+ "dtstsf $BF, $RA, $RB", IIC_FPCompare>;
+
+def DTSTSFQ : XForm_17<63, 674, (outs crrc:$BF), (ins f8rc:$RA, fpairrc:$RB),
+ "dtstsfq $BF, $RA, $RB", IIC_FPCompare>;
+
+def DTSTSFI : XForm_BF3_UIM6_FRB5<59, 675, (outs crrc:$BF),
+ (ins u6imm:$UIM, f8rc:$FRB),
+ "dtstsfi $BF, $UIM, $FRB", IIC_FPCompare, []>;
+
+def DTSTSFIQ : XForm_BF3_UIM6_FRB5<63, 675, (outs crrc:$BF),
+ (ins u6imm:$UIM, fpairrc:$FRB),
+ "dtstsfiq $BF, $UIM, $FRB", IIC_FPCompare, []>;
+
} // hasNoSchedulingInfo
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index f6843c0bc67eda..0081c0f5295a36 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -1221,6 +1221,23 @@ class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Inst{31} = D{5}; // DX
}
+class XForm_BF3_UIM6_FRB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin, list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<3> BF;
+ bits<6> UIM;
+ bits<5> FRB;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = BF;
+ let Inst{9} = 0;
+ let Inst{10-15} = UIM;
+ let Inst{16-20} = FRB;
+ let Inst{21-30} = xo;
+ let Inst{31} = 0;
+}
+
class XForm_SP2_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
list<dag> pattern, InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> {
@@ -2170,6 +2187,24 @@ class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
let Inst{23-31} = xo;
}
+class Z22Form_BF3_FRA5_DCM6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+ string asmstr, InstrItinClass itin,
+ list<dag> pattern>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<3> BF;
+ bits<5> FRA;
+ bits<6> DCM;
+
+ let Pattern = pattern;
+
+ let Inst{6-8} = BF;
+ let Inst{9-10} = 0;
+ let Inst{11-15} = FRA;
+ let Inst{16-21} = DCM;
+ let Inst{22-30} = xo;
+ let Inst{31} = 0;
+}
+
class Z22Form_FRTA5_SH6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
string asmstr, list<dag> pattern, InstrItinClass itin>
: I<opcode, OOL, IOL, asmstr, itin> {
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
index e7db0c10e1e36c..91831b64d44724 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
@@ -245,3 +245,33 @@
# CHECK: dscriq. 16, 10, 50
0xfe 0x0a 0xc8 0xc5
+
+# CHECK: dtstdc 2, 6, 4
+0xed,0x06,0x11,0x84
+
+# CHECK: dtstdcq 2, 6, 4
+0xfd,0x06,0x11,0x84
+
+# CHECK: dtstdg 2, 6, 4
+0xed,0x06,0x11,0xc4
+
+# CHECK: dtstdgq 2, 6, 4
+0xfd,0x06,0x11,0xc4
+
+# CHECK: dtstex 2, 6, 4
+0xed,0x06,0x21,0x44
+
+# CHECK: dtstexq 2, 6, 4
+0xfd,0x06,0x21,0x44
+
+# CHECK: dtstsf 2, 6, 4
+0xed,0x06,0x25,0x44
+
+# CHECK: dtstsfq 2, 6, 4
+0xfd,0x06,0x25,0x44
+
+# CHECK: dtstsfi 2, 6, 4
+0xed,0x06,0x25,0x46
+
+# CHECK: dtstsfiq 2, 6, 4
+0xfd,0x06,0x25,0x46
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
index f59d5f12cb22d9..34ce8875d1c9f3 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
@@ -248,3 +248,33 @@
# CHECK-BE: dscriq. 16, 10, 50 # encoding: [0xfe,0x0a,0xc8,0xc5]
# CHECK-LE: dscriq. 16, 10, 50 # encoding: [0xc5,0xc8,0x0a,0xfe]
dscriq. 16, 10, 50
+# CHECK-BE: dtstdc 2, 6, 4 # encoding: [0xed,0x06,0x11,0x84]
+# CHECK-LE: dtstdc 2, 6, 4 # encoding: [0x84,0x11,0x06,0xed]
+ dtstdc 2, 6, 4
+# CHECK-BE: dtstdcq 2, 6, 4 # encoding: [0xfd,0x06,0x11,0x84]
+# CHECK-LE: dtstdcq 2, 6, 4 # encoding: [0x84,0x11,0x06,0xfd]
+ dtstdcq 2, 6, 4
+# CHECK-BE: dtstdg 2, 6, 4 # encoding: [0xed,0x06,0x11,0xc4]
+# CHECK-LE: dtstdg 2, 6, 4 # encoding: [0xc4,0x11,0x06,0xed]
+ dtstdg 2, 6, 4
+# CHECK-BE: dtstdgq 2, 6, 4 # encoding: [0xfd,0x06,0x11,0xc4]
+# CHECK-LE: dtstdgq 2, 6, 4 # encoding: [0xc4,0x11,0x06,0xfd]
+ dtstdgq 2, 6, 4
+# CHECK-BE: dtstex 2, 6, 4 # encoding: [0xed,0x06,0x21,0x44]
+# CHECK-LE: dtstex 2, 6, 4 # encoding: [0x44,0x21,0x06,0xed]
+ dtstex 2, 6, 4
+# CHECK-BE: dtstexq 2, 6, 4 # encoding: [0xfd,0x06,0x21,0x44]
+# CHECK-LE: dtstexq 2, 6, 4 # encoding: [0x44,0x21,0x06,0xfd]
+ dtstexq 2, 6, 4
+# CHECK-BE: dtstsf 2, 6, 4 # encoding: [0xed,0x06,0x25,0x44]
+# CHECK-LE: dtstsf 2, 6, 4 # encoding: [0x44,0x25,0x06,0xed]
+ dtstsf 2, 6, 4
+# CHECK-BE: dtstsfq 2, 6, 4 # encoding: [0xfd,0x06,0x25,0x44]
+# CHECK-LE: dtstsfq 2, 6, 4 # encoding: [0x44,0x25,0x06,0xfd]
+ dtstsfq 2, 6, 4
+# CHECK-BE: dtstsfi 2, 6, 4 # encoding: [0xed,0x06,0x25,0x46]
+# CHECK-LE: dtstsfi 2, 6, 4 # encoding: [0x46,0x25,0x06,0xed]
+ dtstsfi 2, 6, 4
+# CHECK-BE: dtstsfiq 2, 6, 4 # encoding: [0xfd,0x06,0x25,0x46]
+# CHECK-LE: dtstsfiq 2, 6, 4 # encoding: [0x46,0x25,0x06,0xfd]
+ dtstsfiq 2, 6, 4
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