[PATCH] D153502: [DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns

[Craig Topper via Phabricator via llvm-commits]

craig.topper added inline comments.


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6037
+  // Check if the operands of an and/or operation are comparisons and if they
+  // compare against the same value. Replace, the and/or-cmp-cmp sequence with
+  // min/max cmp sequence. If LHS1 is equal to RHS1, then the or-cmp-cmp
----------------
Remove comma after "Replace"


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6039
+  // min/max cmp sequence. If LHS1 is equal to RHS1, then the or-cmp-cmp
+  // sequrence will be replaced with min-cmp sequence:
+  // (LHS0 < LHS1) | (RHS0 < RHS1) -> min(LHS0, RHS0) < LHS1
----------------
sequence8


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6054
+        // The two comparions should have either the same predicate or the
+        // predicate of one of the comprisons is the opposite of the other one.
+        (CCL == CCR || (CCL == ISD::getSetCCSwappedOperands(CCR))) &&
----------------
comparisons*


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6055
+        // predicate of one of the comprisons is the opposite of the other one.
+        (CCL == CCR || (CCL == ISD::getSetCCSwappedOperands(CCR))) &&
+        // The optimization does not work for `==` or `!=` .
----------------
Drop curly braces around `(CCL == ISD::getSetCCSwappedOperands(CCR))`


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6057
+        // The optimization does not work for `==` or `!=` .
+        CCL != ISD::SETEQ && CCL != ISD::SETNE && CCR != ISD::SETEQ &&
+        CCR != ISD::SETNE) {
----------------
!ISD::isIntEqualitySetCC(CCL) && !ISD::isIntEquality(CCR)


================
Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6059
+        CCR != ISD::SETNE) {
+      if (CCL != ISD::getSetCCSwappedOperands(CCR)) {
+        if (LHS0 == RHS0) {
----------------
Is this the same as CCL == CCR?


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Comment at: llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp:6098
+
+        if (NewOpcode) {
+          SDValue MinMaxValue =
----------------
Can NewOpcode ever be unassigned here?


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D153502/new/

https://reviews.llvm.org/D153502