[llvm] 424392b - [PowerPC] Add DFP format instructions definitions and MC tests
Lei Huang via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 14 09:09:29 PDT 2023
Author: Lei Huang
Date: 2023-07-14T12:09:24-04:00
New Revision: 424392b6960b934bba2687024cf968e0729220b4
URL: https://github.com/llvm/llvm-project/commit/424392b6960b934bba2687024cf968e0729220b4
DIFF: https://github.com/llvm/llvm-project/commit/424392b6960b934bba2687024cf968e0729220b4.diff
LOG: [PowerPC] Add DFP format instructions definitions and MC tests
Add td definitions and asm/disasm tests for the dfp format
instructions in ISA 3.1 section 5.6.6
Reviewed By: stefanp, kamaub
Differential Revision: https://reviews.llvm.org/D154465
Added:
Modified:
llvm/lib/Target/PowerPC/PPCInstrDFP.td
llvm/lib/Target/PowerPC/PPCInstrFormats.td
llvm/lib/Target/PowerPC/PPCInstrInfo.td
llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
Removed:
################################################################################
diff --git a/llvm/lib/Target/PowerPC/PPCInstrDFP.td b/llvm/lib/Target/PowerPC/PPCInstrDFP.td
index 48cfcb4c714d8c..6ce6cb39ea08d6 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrDFP.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrDFP.td
@@ -114,5 +114,42 @@ let RA = 1 in
"dctfixqq $RST, $RB", IIC_FPGeneral, []>;
} // HasP10Vector
+// 5.6.6 DFP Format Instructions
+defm DENBCD: XForm_S1_FRTB5r<59, 834, (outs f8rc:$FRT),
+ (ins u1imm:$S, f8rc:$FRB),
+ "denbcd", "$S, $FRT, $FRB", []>;
+defm DENBCDQ: XForm_S1_FRTB5r<63, 834, (outs fpairrc:$FRT),
+ (ins u1imm:$S, fpairrc:$FRB),
+ "denbcdq", "$S, $FRT, $FRB", []>;
} // mayRaiseFPException
+
+// 5.6.6 DFP none exception raising format instructions.
+defm DDEDPD: XForm_SP2_FRTB5r<59, 322, (outs f8rc:$FRT),
+ (ins u2imm:$SP, f8rc:$FRB),
+ "ddedpd", "$SP, $FRT, $FRB", []>;
+defm DDEDPDQ: XForm_SP2_FRTB5r<63, 322, (outs fpairrc:$FRT),
+ (ins u2imm:$SP, fpairrc:$FRB),
+ "ddedpdq", "$SP, $FRT, $FRB", []>;
+defm DXEX: XForm_26r<59, 354, (outs f8rc:$RST), (ins f8rc:$RB),
+ "dxex", "$RST, $RB", NoItinerary, []>;
+defm DXEXQ: XForm_26r<63, 354, (outs f8rc:$RST), (ins fpairrc:$RB),
+ "dxexq", "$RST, $RB", NoItinerary, []>;
+defm DIEX: XForm_base_r3xo_r<59, 866, (outs f8rc:$RST),
+ (ins f8rc:$RA, f8rc:$RB),
+ "diex", "$RST, $RA, $RB", []>;
+defm DIEXQ: XForm_base_r3xo_r<63, 866, (outs fpairrc:$RST),
+ (ins f8rc:$RA, fpairrc:$RB),
+ "diexq", "$RST, $RA, $RB", []>;
+defm DSCLI: Z22Form_FRTA5_SH6r<59, 66, (outs f8rc:$FRT),
+ (ins f8rc:$FRA, u6imm:$SH),
+ "dscli", "$FRT, $FRA, $SH", []>;
+defm DSCLIQ: Z22Form_FRTA5_SH6r<63, 66, (outs fpairrc:$FRT),
+ (ins fpairrc:$FRA, u6imm:$SH),
+ "dscliq", "$FRT, $FRA, $SH", []>;
+defm DSCRI: Z22Form_FRTA5_SH6r<59, 98, (outs f8rc:$FRT),
+ (ins f8rc:$FRA, u6imm:$SH),
+ "dscri", "$FRT, $FRA, $SH", []>;
+defm DSCRIQ: Z22Form_FRTA5_SH6r<63, 98, (outs fpairrc:$FRT),
+ (ins fpairrc:$FRA, u6imm:$SH),
+ "dscriq", "$FRT, $FRA, $SH", []>;
} // hasNoSchedulingInfo
diff --git a/llvm/lib/Target/PowerPC/PPCInstrFormats.td b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
index a52cf68ba26fbe..f6843c0bc67eda 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrFormats.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrFormats.td
@@ -1221,6 +1221,44 @@ class XForm_XD6_RA5_RB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
let Inst{31} = D{5}; // DX
}
+class XForm_SP2_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL, string asmstr,
+ list<dag> pattern, InstrItinClass itin>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bits<2> SP;
+ bits<5> FRT;
+ bits<5> FRB;
+
+ let Pattern = pattern;
+
+ bit RC = 0; // set by isRecordForm
+
+ let Inst{6 - 10} = FRT;
+ let Inst{11 - 12} = SP;
+ let Inst{13 - 15} = 0;
+ let Inst{16 - 20} = FRB;
+ let Inst{21 - 30} = xo;
+ let Inst{31} = RC;
+}
+
+class XForm_S1_FRTB5<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern, InstrItinClass itin>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+ bit S;
+ bits<5> FRT;
+ bits<5> FRB;
+
+ let Pattern = pattern;
+
+ bit RC = 0; // set by isRecordForm
+
+ let Inst{6 - 10} = FRT;
+ let Inst{11} = S;
+ let Inst{12 - 15} = 0;
+ let Inst{16 - 20} = FRB;
+ let Inst{21 - 30} = xo;
+ let Inst{31} = RC;
+}
+
class XX3Form<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
@@ -2132,6 +2170,25 @@ class VX_RD5_RSp5_PS1_XO9<bits<9> xo, dag OOL, dag IOL, string asmstr,
let Inst{23-31} = xo;
}
+class Z22Form_FRTA5_SH6<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+ string asmstr, list<dag> pattern, InstrItinClass itin>
+ : I<opcode, OOL, IOL, asmstr, itin> {
+
+ bits<5> FRT;
+ bits<5> FRA;
+ bits<6> SH;
+
+ let Pattern = pattern;
+
+ bit RC = 0; // set by isRecordForm
+
+ let Inst{6 - 10} = FRT;
+ let Inst{11 - 15} = FRA;
+ let Inst{16 - 21} = SH;
+ let Inst{22 - 30} = xo;
+ let Inst{31} = RC;
+}
+
class Z23Form_8<bits<6> opcode, bits<8> xo, dag OOL, dag IOL, string asmstr,
InstrItinClass itin, list<dag> pattern>
: I<opcode, OOL, IOL, asmstr, itin> {
diff --git a/llvm/lib/Target/PowerPC/PPCInstrInfo.td b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
index d95fc9b36a47fd..616f4e48cfb88a 100644
--- a/llvm/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/llvm/lib/Target/PowerPC/PPCInstrInfo.td
@@ -730,6 +730,18 @@ def IsNotISAFuture : Predicate<"!Subtarget->isISAFuture()">;
//===----------------------------------------------------------------------===//
// PowerPC Multiclass Definitions.
+multiclass XForm_base_r3xo_r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmbase, string asmstr, list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME : XForm_base_r3xo<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)),
+ NoItinerary, pattern>, RecFormRel;
+ let Defs = [CR1] in
+ def _rec : XForm_base_r3xo<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)),
+ NoItinerary, []>, isRecordForm, RecFormRel;
+ }
+}
multiclass XForm_6r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin,
@@ -1043,6 +1055,32 @@ multiclass XForm_28r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
}
}
+multiclass XForm_SP2_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmbase, string asmstr, list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME : XForm_SP2_FRTB5<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)),
+ pattern, NoItinerary>, RecFormRel;
+ let Defs = [CR1] in
+ def _rec : XForm_SP2_FRTB5<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)),
+ [], NoItinerary>, isRecordForm, RecFormRel;
+ }
+}
+
+multiclass XForm_S1_FRTB5r<bits<6> opcode, bits<10> xo, dag OOL, dag IOL,
+ string asmbase, string asmstr, list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME : XForm_S1_FRTB5<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)),
+ pattern, NoItinerary>, RecFormRel;
+ let Defs = [CR1] in
+ def _rec : XForm_S1_FRTB5<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)), [],
+ NoItinerary>, isRecordForm, RecFormRel;
+ }
+}
+
multiclass AForm_1r<bits<6> opcode, bits<5> xo, dag OOL, dag IOL,
string asmbase, string asmstr, InstrItinClass itin,
list<dag> pattern> {
@@ -1128,6 +1166,19 @@ multiclass
}
}
+multiclass Z22Form_FRTA5_SH6r<bits<6> opcode, bits<9> xo, dag OOL, dag IOL,
+ string asmbase, string asmstr, list<dag> pattern> {
+ let BaseName = asmbase in {
+ def NAME : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(" ", asmstr)),
+ pattern, NoItinerary>, RecFormRel;
+ let Defs = [CR1] in
+ def _rec : Z22Form_FRTA5_SH6<opcode, xo, OOL, IOL,
+ !strconcat(asmbase, !strconcat(". ", asmstr)),
+ [], NoItinerary>, isRecordForm, RecFormRel;
+ }
+}
+
//===----------------------------------------------------------------------===//
// END OF MULTICLASS DEFINITIONS
//===----------------------------------------------------------------------===//
diff --git a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
index 35147bb0f097c5..e7db0c10e1e36c 100644
--- a/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
+++ b/llvm/test/MC/Disassembler/PowerPC/ppc64-encoding-dfp.txt
@@ -173,3 +173,75 @@
# CHECK: dctfixqq 8, 10
0xfd 0x01 0x57 0xc4
+
+# CHECK: ddedpd 0, 8, 10
+0xed 0x00 0x52 0x84
+
+# CHECK: ddedpd. 0, 8, 10
+0xed 0x00 0x52 0x85
+
+# CHECK: ddedpdq 1, 8, 10
+0xfd 0x08 0x52 0x84
+
+# CHECK: ddedpdq. 1, 8, 10
+0xfd 0x08 0x52 0x85
+
+# CHECK: denbcd 1, 12, 16
+0xed 0x90 0x86 0x84
+
+# CHECK: denbcd. 0, 12, 16
+0xed 0x80 0x86 0x85
+
+# CHECK: denbcdq 1, 12, 16
+0xfd 0x90 0x86 0x84
+
+# CHECK: denbcdq. 0, 12, 16
+0xfd 0x80 0x86 0x85
+
+# CHECK: dxex 8, 20
+0xed 0x00 0xa2 0xc4
+
+# CHECK: dxex. 8, 20
+0xed 0x00 0xa2 0xc5
+
+# CHECK: dxexq 8, 20
+0xfd 0x00 0xa2 0xc4
+
+# CHECK: dxexq. 8, 20
+0xfd 0x00 0xa2 0xc5
+
+# CHECK: diex 8, 12, 18
+0xed 0x0c 0x96 0xc4
+
+# CHECK: diex. 8, 12, 18
+0xed 0x0c 0x96 0xc5
+
+# CHECK: diexq. 8, 12, 18
+0xfd 0x0c 0x96 0xc5
+
+# CHECK: diexq 8, 12, 18
+0xfd 0x0c 0x96 0xc4
+
+# CHECK: dscli 22, 4, 63
+0xee 0xc4 0xfc 0x84
+
+# CHECK: dscli. 22, 4, 63
+0xee 0xc4 0xfc 0x85
+
+# CHECK: dscliq 22, 4, 63
+0xfe 0xc4 0xfc 0x84
+
+# CHECK: dscliq. 22, 4, 63
+0xfe 0xc4 0xfc 0x85
+
+# CHECK: dscri 16, 10, 50
+0xee 0x0a 0xc8 0xc4
+
+# CHECK: dscri. 16, 10, 50
+0xee 0x0a 0xc8 0xc5
+
+# CHECK: dscriq 16, 10, 50
+0xfe 0x0a 0xc8 0xc4
+
+# CHECK: dscriq. 16, 10, 50
+0xfe 0x0a 0xc8 0xc5
diff --git a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
index ac7cf55253cb11..f59d5f12cb22d9 100644
--- a/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
+++ b/llvm/test/MC/PowerPC/ppc64-encoding-dfp.s
@@ -176,3 +176,75 @@
# CHECK-LE: dctfixqq 8, 10 # encoding: [0xc4,0x57,0x01,0xfd]
# CHECK-BE: dctfixqq 8, 10 # encoding: [0xfd,0x01,0x57,0xc4]
dctfixqq 8, 10
+# CHECK-BE: ddedpd 0, 8, 10 # encoding: [0xed,0x00,0x52,0x84]
+# CHECK-LE: ddedpd 0, 8, 10 # encoding: [0x84,0x52,0x00,0xed]
+ ddedpd 0, 8, 10
+# CHECK-BE: ddedpd. 0, 8, 10 # encoding: [0xed,0x00,0x52,0x85]
+# CHECK-LE: ddedpd. 0, 8, 10 # encoding: [0x85,0x52,0x00,0xed]
+ ddedpd. 0, 8, 10
+# CHECK-BE: ddedpdq 1, 8, 10 # encoding: [0xfd,0x08,0x52,0x84]
+# CHECK-LE: ddedpdq 1, 8, 10 # encoding: [0x84,0x52,0x08,0xfd]
+ ddedpdq 1, 8, 10
+# CHECK-BE: ddedpdq. 1, 8, 10 # encoding: [0xfd,0x08,0x52,0x85]
+# CHECK-LE: ddedpdq. 1, 8, 10 # encoding: [0x85,0x52,0x08,0xfd]
+ ddedpdq. 1, 8, 10
+# CHECK-BE: denbcd 1, 12, 16 # encoding: [0xed,0x90,0x86,0x84]
+# CHECK-LE: denbcd 1, 12, 16 # encoding: [0x84,0x86,0x90,0xed]
+ denbcd 1, 12, 16
+# CHECK-BE: denbcd. 0, 12, 16 # encoding: [0xed,0x80,0x86,0x85]
+# CHECK-LE: denbcd. 0, 12, 16 # encoding: [0x85,0x86,0x80,0xed]
+ denbcd. 0, 12, 16
+# CHECK-BE: denbcdq 1, 12, 16 # encoding: [0xfd,0x90,0x86,0x84]
+# CHECK-LE: denbcdq 1, 12, 16 # encoding: [0x84,0x86,0x90,0xfd]
+ denbcdq 1, 12, 16
+# CHECK-BE: denbcdq. 0, 12, 16 # encoding: [0xfd,0x80,0x86,0x85]
+# CHECK-LE: denbcdq. 0, 12, 16 # encoding: [0x85,0x86,0x80,0xfd]
+ denbcdq. 0, 12, 16
+# CHECK-BE: dxex 8, 20 # encoding: [0xed,0x00,0xa2,0xc4]
+# CHECK-LE: dxex 8, 20 # encoding: [0xc4,0xa2,0x00,0xed]
+ dxex 8, 20
+# CHECK-BE: dxex. 8, 20 # encoding: [0xed,0x00,0xa2,0xc5]
+# CHECK-LE: dxex. 8, 20 # encoding: [0xc5,0xa2,0x00,0xed]
+ dxex. 8, 20
+# CHECK-BE: dxexq 8, 20 # encoding: [0xfd,0x00,0xa2,0xc4]
+# CHECK-LE: dxexq 8, 20 # encoding: [0xc4,0xa2,0x00,0xfd]
+ dxexq 8, 20
+# CHECK-BE: dxexq. 8, 20 # encoding: [0xfd,0x00,0xa2,0xc5]
+# CHECK-LE: dxexq. 8, 20 # encoding: [0xc5,0xa2,0x00,0xfd]
+ dxexq. 8, 20
+# CHECK-BE: diex 8, 12, 18 # encoding: [0xed,0x0c,0x96,0xc4]
+# CHECK-LE: diex 8, 12, 18 # encoding: [0xc4,0x96,0x0c,0xed]
+ diex 8, 12, 18
+# CHECK-BE: diex. 8, 12, 18 # encoding: [0xed,0x0c,0x96,0xc5]
+# CHECK-LE: diex. 8, 12, 18 # encoding: [0xc5,0x96,0x0c,0xed]
+ diex. 8, 12, 18
+# CHECK-BE: diexq 8, 12, 18 # encoding: [0xfd,0x0c,0x96,0xc4]
+# CHECK-LE: diexq 8, 12, 18 # encoding: [0xc4,0x96,0x0c,0xfd]
+ diexq 8, 12, 18
+# CHECK-BE: diexq. 8, 12, 18 # encoding: [0xfd,0x0c,0x96,0xc5]
+# CHECK-LE: diexq. 8, 12, 18 # encoding: [0xc5,0x96,0x0c,0xfd]
+ diexq. 8, 12, 18
+# CHECK-BE: dscli 22, 4, 63 # encoding: [0xee,0xc4,0xfc,0x84]
+# CHECK-LE: dscli 22, 4, 63 # encoding: [0x84,0xfc,0xc4,0xee]
+ dscli 22, 4, 63
+# CHECK-BE: dscli. 22, 4, 63 # encoding: [0xee,0xc4,0xfc,0x85]
+# CHECK-LE: dscli. 22, 4, 63 # encoding: [0x85,0xfc,0xc4,0xee]
+ dscli. 22, 4, 63
+# CHECK-BE: dscliq 22, 4, 63 # encoding: [0xfe,0xc4,0xfc,0x84]
+# CHECK-LE: dscliq 22, 4, 63 # encoding: [0x84,0xfc,0xc4,0xfe]
+ dscliq 22, 4, 63
+# CHECK-BE: dscliq. 22, 4, 63 # encoding: [0xfe,0xc4,0xfc,0x85]
+# CHECK-LE: dscliq. 22, 4, 63 # encoding: [0x85,0xfc,0xc4,0xfe]
+ dscliq. 22, 4, 63
+# CHECK-BE: dscri 16, 10, 50 # encoding: [0xee,0x0a,0xc8,0xc4]
+# CHECK-LE: dscri 16, 10, 50 # encoding: [0xc4,0xc8,0x0a,0xee]
+ dscri 16, 10, 50
+# CHECK-BE: dscri. 16, 10, 50 # encoding: [0xee,0x0a,0xc8,0xc5]
+# CHECK-LE: dscri. 16, 10, 50 # encoding: [0xc5,0xc8,0x0a,0xee]
+ dscri. 16, 10, 50
+# CHECK-BE: dscriq 16, 10, 50 # encoding: [0xfe,0x0a,0xc8,0xc4]
+# CHECK-LE: dscriq 16, 10, 50 # encoding: [0xc4,0xc8,0x0a,0xfe]
+ dscriq 16, 10, 50
+# CHECK-BE: dscriq. 16, 10, 50 # encoding: [0xfe,0x0a,0xc8,0xc5]
+# CHECK-LE: dscriq. 16, 10, 50 # encoding: [0xc5,0xc8,0x0a,0xfe]
+ dscriq. 16, 10, 50
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