[llvm] 2182726 - [InstCombine] Fold add of zext and sext of i1

[Nikita Popov via llvm-commits]

Author: Nikita Popov
Date: 2023-07-14T14:52:13+02:00
New Revision: 21827268ada2ee62eaee49fcfa1133ed06a63d25

URL: https://github.com/llvm/llvm-project/commit/21827268ada2ee62eaee49fcfa1133ed06a63d25
DIFF: https://github.com/llvm/llvm-project/commit/21827268ada2ee62eaee49fcfa1133ed06a63d25.diff

LOG: [InstCombine] Fold add of zext and sext of i1

(zext a) + (sext a) is 0 if a is a bool.

The regression is in a fuzzer-generated test.

Proof: https://alive2.llvm.org/ce/z/KotnN6

Added: 
    

Modified: 
    llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
    llvm/test/Transforms/InstCombine/add.ll
    llvm/test/Transforms/InstCombine/shift.ll

Removed: 
    


################################################################################
diff  --git a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
index 4c437c29bbc411..cd47a8b5330300 100644
--- a/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
+++ b/llvm/lib/Transforms/InstCombine/InstCombineAddSub.cpp
@@ -1479,6 +1479,11 @@ Instruction *InstCombinerImpl::visitAdd(BinaryOperator &I) {
        match(RHS, m_ZExt(m_NUWSub(m_Value(B), m_Specific(A))))))
     return new ZExtInst(B, LHS->getType());
 
+  // zext(A) + sext(A) --> 0 if A is i1
+  if (match(&I, m_c_BinOp(m_ZExt(m_Value(A)), m_SExt(m_Deferred(A)))) &&
+      A->getType()->isIntOrIntVectorTy(1))
+    return replaceInstUsesWith(I, Constant::getNullValue(I.getType()));
+
   // A+B --> A|B iff A and B have no bits set in common.
   if (haveNoCommonBitsSet(LHS, RHS, DL, &AC, &I, &DT))
     return BinaryOperator::CreateOr(LHS, RHS);

diff  --git a/llvm/test/Transforms/InstCombine/add.ll b/llvm/test/Transforms/InstCombine/add.ll
index 27243d5f4aa489..3ba01fbce0ba6a 100644
--- a/llvm/test/Transforms/InstCombine/add.ll
+++ b/llvm/test/Transforms/InstCombine/add.ll
@@ -3021,10 +3021,7 @@ define <2 x i32> @dec_zext_add_nonzero_vec_poison2(<2 x i8> %x) {
 
 define i32 @add_zext_sext_i1(i1 %a) {
 ; CHECK-LABEL: @add_zext_sext_i1(
-; CHECK-NEXT:    [[ZEXT:%.*]] = zext i1 [[A:%.*]] to i32
-; CHECK-NEXT:    [[SEXT:%.*]] = sext i1 [[A]] to i32
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[ZEXT]], [[SEXT]]
-; CHECK-NEXT:    ret i32 [[ADD]]
+; CHECK-NEXT:    ret i32 0
 ;
   %zext = zext i1 %a to i32
   %sext = sext i1 %a to i32
@@ -3034,10 +3031,7 @@ define i32 @add_zext_sext_i1(i1 %a) {
 
 define i32 @add_sext_zext_i1(i1 %a) {
 ; CHECK-LABEL: @add_sext_zext_i1(
-; CHECK-NEXT:    [[ZEXT:%.*]] = zext i1 [[A:%.*]] to i32
-; CHECK-NEXT:    [[SEXT:%.*]] = sext i1 [[A]] to i32
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw i32 [[SEXT]], [[ZEXT]]
-; CHECK-NEXT:    ret i32 [[ADD]]
+; CHECK-NEXT:    ret i32 0
 ;
   %zext = zext i1 %a to i32
   %sext = sext i1 %a to i32
@@ -3047,10 +3041,7 @@ define i32 @add_sext_zext_i1(i1 %a) {
 
 define <2 x i32> @add_zext_sext_i1_vec(<2 x i1> %a) {
 ; CHECK-LABEL: @add_zext_sext_i1_vec(
-; CHECK-NEXT:    [[ZEXT:%.*]] = zext <2 x i1> [[A:%.*]] to <2 x i32>
-; CHECK-NEXT:    [[SEXT:%.*]] = sext <2 x i1> [[A]] to <2 x i32>
-; CHECK-NEXT:    [[ADD:%.*]] = add nsw <2 x i32> [[ZEXT]], [[SEXT]]
-; CHECK-NEXT:    ret <2 x i32> [[ADD]]
+; CHECK-NEXT:    ret <2 x i32> zeroinitializer
 ;
   %zext = zext <2 x i1> %a to <2 x i32>
   %sext = sext <2 x i1> %a to <2 x i32>

diff  --git a/llvm/test/Transforms/InstCombine/shift.ll b/llvm/test/Transforms/InstCombine/shift.ll
index ede8c8c5c8f7be..3db759ceccb818 100644
--- a/llvm/test/Transforms/InstCombine/shift.ll
+++ b/llvm/test/Transforms/InstCombine/shift.ll
@@ -1689,6 +1689,10 @@ define i177 @lshr_out_of_range(i177 %Y, ptr %A2, ptr %ptr) {
 ; https://bugs.chromium.org/p/oss-fuzz/issues/detail?id=26716
 define i177 @lshr_out_of_range2(i177 %Y, ptr %A2, ptr %ptr) {
 ; CHECK-LABEL: @lshr_out_of_range2(
+; CHECK-NEXT:    [[C8:%.*]] = icmp ne i177 [[Y:%.*]], 0
+; CHECK-NEXT:    [[TMP1:%.*]] = sext i1 [[C8]] to i64
+; CHECK-NEXT:    [[G18:%.*]] = getelementptr ptr, ptr [[A2:%.*]], i64 [[TMP1]]
+; CHECK-NEXT:    store ptr [[G18]], ptr [[PTR:%.*]], align 8
 ; CHECK-NEXT:    ret i177 0
 ;
   %B5 = udiv i177 %Y, -1