[PATCH] D155288: [RISCV] Add a new select combine for when the condition is a setcc that will be inverted

[Alex Bradbury via Phabricator via llvm-commits]

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This is primarily motivated by improving codegen for zicond (fixing the code quality regressions knowingly introduced in D155083 <https://reviews.llvm.org/D155083>), but the combine is enabled regardless of the presence of zicond as it appears to be either neutral or provide minor benefits even without zicond.

      

Because we lower select early (due to it not being a legal operation), we miss out on some of the select combines that would kick in after other operations have been legalised - in this case if the condval is a setcc that will later be inverted when being legalised, the xori instruction can be removed just by flipping the TrueVal and FalseVal. This combine just performs that transformation.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155288

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/test/CodeGen/RISCV/atomic-rmw.ll
  llvm/test/CodeGen/RISCV/atomic-signext.ll
  llvm/test/CodeGen/RISCV/atomicrmw-uinc-udec-wrap.ll
  llvm/test/CodeGen/RISCV/compress.ll
  llvm/test/CodeGen/RISCV/condops.ll
  llvm/test/CodeGen/RISCV/double-select-icmp.ll
  llvm/test/CodeGen/RISCV/float-select-icmp.ll
  llvm/test/CodeGen/RISCV/forced-atomics.ll
  llvm/test/CodeGen/RISCV/half-select-icmp.ll
  llvm/test/CodeGen/RISCV/select-cc.ll
  llvm/test/CodeGen/RISCV/select-constant-xor.ll
  llvm/test/CodeGen/RISCV/xaluo.ll

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