[PATCH] D152706: [AMDGPU] Use SSAUpdater in PromoteAlloca
Pierre van Houtryve via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Fri Jul 14 00:10:57 PDT 2023
Pierre-vh marked 3 inline comments as done.
Pierre-vh added inline comments.
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Comment at: llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll:67
%alloca.val = alloca <8 x i32>, align 64, addrspace(5)
store volatile <8 x i32> %val, ptr addrspace(5) %alloca.val, align 64
call void asm sideeffect "", "~{v40}" ()
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arsenm wrote:
> Why did this change? It only uses volatile accesses
We support non-simple accesses of the whole vector, it's volatile accesses of a single element that we don't support
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Comment at: llvm/test/CodeGen/AMDGPU/promote-alloca-loadstores.ll:127
+; Currently rejected due to the store not being cast-able.
+; TODO: We should probably be able to vectorize this
+define void @alloca_load_store_ptr_mixed_ptrvec(<2 x ptr addrspace(3)> %arg) {
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arsenm wrote:
> There was a recent bug filed that amounts to not handling this (it didn't use pointers, but just different sized vectors)
Yes, I just saw it. I'd rather fix this in a separate patch; this patch is already quite large and if I do too much in it I'm afraid it'll make potential issues harder to track down
I think we just need to use something else than `isBitOrNoopPointerCastable`. It's too limited because it doesn't take into account that we can use an intermediate cast (like the cast to int for ptr -> vec)
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D152706/new/
https://reviews.llvm.org/D152706
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