[llvm] 5141a52 - [ARM] Replace OperandMatchResultTy with ParseStatus (NFC)
Sergei Barannikov via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 13 16:31:23 PDT 2023
Author: Sergei Barannikov
Date: 2023-07-14T02:31:05+03:00
New Revision: 5141a520b04fc3f0efa741df9253db7d78bb3271
URL: https://github.com/llvm/llvm-project/commit/5141a520b04fc3f0efa741df9253db7d78bb3271
DIFF: https://github.com/llvm/llvm-project/commit/5141a520b04fc3f0efa741df9253db7d78bb3271.diff
LOG: [ARM] Replace OperandMatchResultTy with ParseStatus (NFC)
ParseStatus is slightly more convenient to use due to implicit
conversion from bool, which allows to do something like:
```
return Error(L, "msg");
```
when with MatchOperandResultTy it had to be:
```
Error(L, "msg");
return MatchOperand_ParseFail;
```
It also has more appropriate name since parse* methods are not only for
parsing operands.
Reviewed By: olista01
Differential Revision: https://reviews.llvm.org/D154304
Added:
Modified:
llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
Removed:
################################################################################
diff --git a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
index 234503b7b46bcd..ef4c70916eeb5d 100644
--- a/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
+++ b/llvm/lib/Target/ARM/AsmParser/ARMAsmParser.cpp
@@ -623,35 +623,34 @@ class ARMAsmParser : public MCTargetAsmParser {
/// }
- OperandMatchResultTy parseITCondCode(OperandVector &);
- OperandMatchResultTy parseCoprocNumOperand(OperandVector &);
- OperandMatchResultTy parseCoprocRegOperand(OperandVector &);
- OperandMatchResultTy parseCoprocOptionOperand(OperandVector &);
- OperandMatchResultTy parseMemBarrierOptOperand(OperandVector &);
- OperandMatchResultTy parseTraceSyncBarrierOptOperand(OperandVector &);
- OperandMatchResultTy parseInstSyncBarrierOptOperand(OperandVector &);
- OperandMatchResultTy parseProcIFlagsOperand(OperandVector &);
- OperandMatchResultTy parseMSRMaskOperand(OperandVector &);
- OperandMatchResultTy parseBankedRegOperand(OperandVector &);
- OperandMatchResultTy parsePKHImm(OperandVector &O, StringRef Op, int Low,
- int High);
- OperandMatchResultTy parsePKHLSLImm(OperandVector &O) {
+ ParseStatus parseITCondCode(OperandVector &);
+ ParseStatus parseCoprocNumOperand(OperandVector &);
+ ParseStatus parseCoprocRegOperand(OperandVector &);
+ ParseStatus parseCoprocOptionOperand(OperandVector &);
+ ParseStatus parseMemBarrierOptOperand(OperandVector &);
+ ParseStatus parseTraceSyncBarrierOptOperand(OperandVector &);
+ ParseStatus parseInstSyncBarrierOptOperand(OperandVector &);
+ ParseStatus parseProcIFlagsOperand(OperandVector &);
+ ParseStatus parseMSRMaskOperand(OperandVector &);
+ ParseStatus parseBankedRegOperand(OperandVector &);
+ ParseStatus parsePKHImm(OperandVector &O, StringRef Op, int Low, int High);
+ ParseStatus parsePKHLSLImm(OperandVector &O) {
return parsePKHImm(O, "lsl", 0, 31);
}
- OperandMatchResultTy parsePKHASRImm(OperandVector &O) {
+ ParseStatus parsePKHASRImm(OperandVector &O) {
return parsePKHImm(O, "asr", 1, 32);
}
- OperandMatchResultTy parseSetEndImm(OperandVector &);
- OperandMatchResultTy parseShifterImm(OperandVector &);
- OperandMatchResultTy parseRotImm(OperandVector &);
- OperandMatchResultTy parseModImm(OperandVector &);
- OperandMatchResultTy parseBitfield(OperandVector &);
- OperandMatchResultTy parsePostIdxReg(OperandVector &);
- OperandMatchResultTy parseAM3Offset(OperandVector &);
- OperandMatchResultTy parseFPImm(OperandVector &);
- OperandMatchResultTy parseVectorList(OperandVector &);
- OperandMatchResultTy parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
- SMLoc &EndLoc);
+ ParseStatus parseSetEndImm(OperandVector &);
+ ParseStatus parseShifterImm(OperandVector &);
+ ParseStatus parseRotImm(OperandVector &);
+ ParseStatus parseModImm(OperandVector &);
+ ParseStatus parseBitfield(OperandVector &);
+ ParseStatus parsePostIdxReg(OperandVector &);
+ ParseStatus parseAM3Offset(OperandVector &);
+ ParseStatus parseFPImm(OperandVector &);
+ ParseStatus parseVectorList(OperandVector &);
+ ParseStatus parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index,
+ SMLoc &EndLoc);
// Asm Match Converter Methods
void cvtThumbMultiply(MCInst &Inst, const OperandVector &);
@@ -4327,98 +4326,91 @@ static int MatchCoprocessorOperandName(StringRef Name, char CoprocOp) {
}
/// parseITCondCode - Try to parse a condition code for an IT instruction.
-OperandMatchResultTy
-ARMAsmParser::parseITCondCode(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseITCondCode(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
if (!Tok.is(AsmToken::Identifier))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
unsigned CC = ARMCondCodeFromString(Tok.getString());
if (CC == ~0U)
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat the token.
Operands.push_back(ARMOperand::CreateCondCode(ARMCC::CondCodes(CC), S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// parseCoprocNumOperand - Try to parse an coprocessor number operand. The
/// token must be an Identifier when called, and if it is a coprocessor
/// number, the token is eaten and the operand is added to the operand list.
-OperandMatchResultTy
-ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseCoprocNumOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
if (Tok.isNot(AsmToken::Identifier))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
int Num = MatchCoprocessorOperandName(Tok.getString().lower(), 'p');
if (Num == -1)
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
if (!isValidCoprocessorNumber(Num, getSTI().getFeatureBits()))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat identifier token.
Operands.push_back(ARMOperand::CreateCoprocNum(Num, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// parseCoprocRegOperand - Try to parse an coprocessor register operand. The
/// token must be an Identifier when called, and if it is a coprocessor
/// number, the token is eaten and the operand is added to the operand list.
-OperandMatchResultTy
-ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseCoprocRegOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
if (Tok.isNot(AsmToken::Identifier))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
int Reg = MatchCoprocessorOperandName(Tok.getString().lower(), 'c');
if (Reg == -1)
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat identifier token.
Operands.push_back(ARMOperand::CreateCoprocReg(Reg, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// parseCoprocOptionOperand - Try to parse an coprocessor option operand.
/// coproc_option : '{' imm0_255 '}'
-OperandMatchResultTy
-ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseCoprocOptionOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
// If this isn't a '{', this isn't a coprocessor immediate operand.
if (Parser.getTok().isNot(AsmToken::LCurly))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat the '{'
const MCExpr *Expr;
SMLoc Loc = Parser.getTok().getLoc();
- if (getParser().parseExpression(Expr)) {
- Error(Loc, "illegal expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(Expr))
+ return Error(Loc, "illegal expression");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Expr);
- if (!CE || CE->getValue() < 0 || CE->getValue() > 255) {
- Error(Loc, "coprocessor option must be an immediate in range [0, 255]");
- return MatchOperand_ParseFail;
- }
+ if (!CE || CE->getValue() < 0 || CE->getValue() > 255)
+ return Error(Loc,
+ "coprocessor option must be an immediate in range [0, 255]");
int Val = CE->getValue();
// Check for and consume the closing '}'
if (Parser.getTok().isNot(AsmToken::RCurly))
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
SMLoc E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat the '}'
Operands.push_back(ARMOperand::CreateCoprocOption(Val, S, E));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
// For register list parsing, we need to map from raw GPR register numbering
@@ -4632,8 +4624,8 @@ bool ARMAsmParser::parseRegisterList(OperandVector &Operands, bool EnforceOrder,
}
// Helper function to parse the lane index for vector lists.
-OperandMatchResultTy ARMAsmParser::
-parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
+ParseStatus ARMAsmParser::parseVectorLane(VectorLaneTy &LaneKind,
+ unsigned &Index, SMLoc &EndLoc) {
MCAsmParser &Parser = getParser();
Index = 0; // Always return a defined index value.
if (Parser.getTok().is(AsmToken::LBrac)) {
@@ -4643,7 +4635,7 @@ parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
LaneKind = AllLanes;
EndLoc = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat the ']'.
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
// There's an optional '#' token here. Normally there wouldn't be, but
@@ -4653,39 +4645,30 @@ parseVectorLane(VectorLaneTy &LaneKind, unsigned &Index, SMLoc &EndLoc) {
const MCExpr *LaneIndex;
SMLoc Loc = Parser.getTok().getLoc();
- if (getParser().parseExpression(LaneIndex)) {
- Error(Loc, "illegal expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(LaneIndex))
+ return Error(Loc, "illegal expression");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LaneIndex);
- if (!CE) {
- Error(Loc, "lane index must be empty or an integer");
- return MatchOperand_ParseFail;
- }
- if (Parser.getTok().isNot(AsmToken::RBrac)) {
- Error(Parser.getTok().getLoc(), "']' expected");
- return MatchOperand_ParseFail;
- }
+ if (!CE)
+ return Error(Loc, "lane index must be empty or an integer");
+ if (Parser.getTok().isNot(AsmToken::RBrac))
+ return Error(Parser.getTok().getLoc(), "']' expected");
EndLoc = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat the ']'.
int64_t Val = CE->getValue();
// FIXME: Make this range check context sensitive for .8, .16, .32.
- if (Val < 0 || Val > 7) {
- Error(Parser.getTok().getLoc(), "lane index out of range");
- return MatchOperand_ParseFail;
- }
+ if (Val < 0 || Val > 7)
+ return Error(Parser.getTok().getLoc(), "lane index out of range");
Index = Val;
LaneKind = IndexedLane;
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
LaneKind = NoLanes;
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
// parse a vector register list
-OperandMatchResultTy
-ARMAsmParser::parseVectorList(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseVectorList(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
VectorLaneTy LaneKind;
unsigned LaneIndex;
@@ -4697,10 +4680,10 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
SMLoc E = Parser.getTok().getEndLoc();
int Reg = tryParseRegister();
if (Reg == -1)
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) {
- OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
- if (Res != MatchOperand_Success)
+ ParseStatus Res = parseVectorLane(LaneKind, LaneIndex, E);
+ if (!Res.isSuccess())
return Res;
switch (LaneKind) {
case NoLanes:
@@ -4716,12 +4699,12 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
false, S, E));
break;
}
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
Reg = getDRegFromQReg(Reg);
- OperandMatchResultTy Res = parseVectorLane(LaneKind, LaneIndex, E);
- if (Res != MatchOperand_Success)
+ ParseStatus Res = parseVectorLane(LaneKind, LaneIndex, E);
+ if (!Res.isSuccess())
return Res;
switch (LaneKind) {
case NoLanes:
@@ -4741,31 +4724,27 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
false, S, E));
break;
}
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
- Error(S, "vector register expected");
- return MatchOperand_ParseFail;
+ return Error(S, "vector register expected");
}
if (Parser.getTok().isNot(AsmToken::LCurly))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat '{' token.
SMLoc RegLoc = Parser.getTok().getLoc();
int Reg = tryParseRegister();
- if (Reg == -1) {
- Error(RegLoc, "register expected");
- return MatchOperand_ParseFail;
- }
+ if (Reg == -1)
+ return Error(RegLoc, "register expected");
unsigned Count = 1;
int Spacing = 0;
unsigned FirstReg = Reg;
- if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
- Error(Parser.getTok().getLoc(), "vector register in range Q0-Q7 expected");
- return MatchOperand_ParseFail;
- }
+ if (hasMVE() && !ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg))
+ return Error(Parser.getTok().getLoc(),
+ "vector register in range Q0-Q7 expected");
// The list is of D registers, but we also allow Q regs and just interpret
// them as the two D sub-registers.
else if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
@@ -4777,26 +4756,22 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
}
SMLoc E;
- if (parseVectorLane(LaneKind, LaneIndex, E) != MatchOperand_Success)
- return MatchOperand_ParseFail;
+ if (!parseVectorLane(LaneKind, LaneIndex, E).isSuccess())
+ return ParseStatus::Failure;
while (Parser.getTok().is(AsmToken::Comma) ||
Parser.getTok().is(AsmToken::Minus)) {
if (Parser.getTok().is(AsmToken::Minus)) {
if (!Spacing)
Spacing = 1; // Register range implies a single spaced list.
- else if (Spacing == 2) {
- Error(Parser.getTok().getLoc(),
- "sequential registers in double spaced list");
- return MatchOperand_ParseFail;
- }
+ else if (Spacing == 2)
+ return Error(Parser.getTok().getLoc(),
+ "sequential registers in double spaced list");
Parser.Lex(); // Eat the minus.
SMLoc AfterMinusLoc = Parser.getTok().getLoc();
int EndReg = tryParseRegister();
- if (EndReg == -1) {
- Error(AfterMinusLoc, "register expected");
- return MatchOperand_ParseFail;
- }
+ if (EndReg == -1)
+ return Error(AfterMinusLoc, "register expected");
// Allow Q regs and just interpret them as the two D sub-registers.
if (!hasMVE() && ARMMCRegisterClasses[ARM::QPRRegClassID].contains(EndReg))
EndReg = getDRegFromQReg(EndReg) + 1;
@@ -4808,25 +4783,18 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
if ((hasMVE() &&
!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(EndReg)) ||
(!hasMVE() &&
- !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg))) {
- Error(AfterMinusLoc, "invalid register in register list");
- return MatchOperand_ParseFail;
- }
+ !ARMMCRegisterClasses[ARM::DPRRegClassID].contains(EndReg)))
+ return Error(AfterMinusLoc, "invalid register in register list");
// Ranges must go from low to high.
- if (Reg > EndReg) {
- Error(AfterMinusLoc, "bad range in register list");
- return MatchOperand_ParseFail;
- }
+ if (Reg > EndReg)
+ return Error(AfterMinusLoc, "bad range in register list");
// Parse the lane specifier if present.
VectorLaneTy NextLaneKind;
unsigned NextLaneIndex;
- if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
- MatchOperand_Success)
- return MatchOperand_ParseFail;
- if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
- Error(AfterMinusLoc, "mismatched lane index in register list");
- return MatchOperand_ParseFail;
- }
+ if (!parseVectorLane(NextLaneKind, NextLaneIndex, E).isSuccess())
+ return ParseStatus::Failure;
+ if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex)
+ return Error(AfterMinusLoc, "mismatched lane index in register list");
// Add all the registers in the range to the register list.
Count += EndReg - Reg;
@@ -4837,16 +4805,12 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
RegLoc = Parser.getTok().getLoc();
int OldReg = Reg;
Reg = tryParseRegister();
- if (Reg == -1) {
- Error(RegLoc, "register expected");
- return MatchOperand_ParseFail;
- }
+ if (Reg == -1)
+ return Error(RegLoc, "register expected");
if (hasMVE()) {
- if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg)) {
- Error(RegLoc, "vector register in range Q0-Q7 expected");
- return MatchOperand_ParseFail;
- }
+ if (!ARMMCRegisterClasses[ARM::MQPRRegClassID].contains(Reg))
+ return Error(RegLoc, "vector register in range Q0-Q7 expected");
Spacing = 1;
}
// vector register lists must be contiguous.
@@ -4858,29 +4822,23 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
else if (ARMMCRegisterClasses[ARM::QPRRegClassID].contains(Reg)) {
if (!Spacing)
Spacing = 1; // Register range implies a single spaced list.
- else if (Spacing == 2) {
- Error(RegLoc,
- "invalid register in double-spaced list (must be 'D' register')");
- return MatchOperand_ParseFail;
- }
+ else if (Spacing == 2)
+ return Error(
+ RegLoc,
+ "invalid register in double-spaced list (must be 'D' register')");
Reg = getDRegFromQReg(Reg);
- if (Reg != OldReg + 1) {
- Error(RegLoc, "non-contiguous register range");
- return MatchOperand_ParseFail;
- }
+ if (Reg != OldReg + 1)
+ return Error(RegLoc, "non-contiguous register range");
++Reg;
Count += 2;
// Parse the lane specifier if present.
VectorLaneTy NextLaneKind;
unsigned NextLaneIndex;
SMLoc LaneLoc = Parser.getTok().getLoc();
- if (parseVectorLane(NextLaneKind, NextLaneIndex, E) !=
- MatchOperand_Success)
- return MatchOperand_ParseFail;
- if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
- Error(LaneLoc, "mismatched lane index in register list");
- return MatchOperand_ParseFail;
- }
+ if (!parseVectorLane(NextLaneKind, NextLaneIndex, E).isSuccess())
+ return ParseStatus::Failure;
+ if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex)
+ return Error(LaneLoc, "mismatched lane index in register list");
continue;
}
// Normal D register.
@@ -4890,27 +4848,21 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
Spacing = 1 + (Reg == OldReg + 2);
// Just check that it's contiguous and keep going.
- if (Reg != OldReg + Spacing) {
- Error(RegLoc, "non-contiguous register range");
- return MatchOperand_ParseFail;
- }
+ if (Reg != OldReg + Spacing)
+ return Error(RegLoc, "non-contiguous register range");
++Count;
// Parse the lane specifier if present.
VectorLaneTy NextLaneKind;
unsigned NextLaneIndex;
SMLoc EndLoc = Parser.getTok().getLoc();
- if (parseVectorLane(NextLaneKind, NextLaneIndex, E) != MatchOperand_Success)
- return MatchOperand_ParseFail;
- if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex) {
- Error(EndLoc, "mismatched lane index in register list");
- return MatchOperand_ParseFail;
- }
+ if (!parseVectorLane(NextLaneKind, NextLaneIndex, E).isSuccess())
+ return ParseStatus::Failure;
+ if (NextLaneKind != LaneKind || LaneIndex != NextLaneIndex)
+ return Error(EndLoc, "mismatched lane index in register list");
}
- if (Parser.getTok().isNot(AsmToken::RCurly)) {
- Error(Parser.getTok().getLoc(), "'}' expected");
- return MatchOperand_ParseFail;
- }
+ if (Parser.getTok().isNot(AsmToken::RCurly))
+ return Error(Parser.getTok().getLoc(), "'}' expected");
E = Parser.getTok().getEndLoc();
Parser.Lex(); // Eat '}' token.
@@ -4937,12 +4889,11 @@ ARMAsmParser::parseVectorList(OperandVector &Operands) {
S, E));
break;
}
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// parseMemBarrierOptOperand - Try to parse DSB/DMB data barrier options.
-OperandMatchResultTy
-ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
@@ -4976,7 +4927,7 @@ ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
Opt = ~0U;
if (Opt == ~0U)
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat identifier token.
} else if (Tok.is(AsmToken::Hash) ||
@@ -4987,51 +4938,45 @@ ARMAsmParser::parseMemBarrierOptOperand(OperandVector &Operands) {
SMLoc Loc = Parser.getTok().getLoc();
const MCExpr *MemBarrierID;
- if (getParser().parseExpression(MemBarrierID)) {
- Error(Loc, "illegal expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(MemBarrierID))
+ return Error(Loc, "illegal expression");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(MemBarrierID);
- if (!CE) {
- Error(Loc, "constant expression expected");
- return MatchOperand_ParseFail;
- }
+ if (!CE)
+ return Error(Loc, "constant expression expected");
int Val = CE->getValue();
- if (Val & ~0xf) {
- Error(Loc, "immediate value out of range");
- return MatchOperand_ParseFail;
- }
+ if (Val & ~0xf)
+ return Error(Loc, "immediate value out of range");
Opt = ARM_MB::RESERVED_0 + Val;
} else
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
Operands.push_back(ARMOperand::CreateMemBarrierOpt((ARM_MB::MemBOpt)Opt, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
-OperandMatchResultTy
+ParseStatus
ARMAsmParser::parseTraceSyncBarrierOptOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
if (Tok.isNot(AsmToken::Identifier))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
if (!Tok.getString().equals_insensitive("csync"))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat identifier token.
Operands.push_back(ARMOperand::CreateTraceSyncBarrierOpt(ARM_TSB::CSYNC, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// parseInstSyncBarrierOptOperand - Try to parse ISB inst sync barrier options.
-OperandMatchResultTy
+ParseStatus
ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
@@ -5044,7 +4989,7 @@ ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
if (OptStr.equals_insensitive("sy"))
Opt = ARM_ISB::SY;
else
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat identifier token.
} else if (Tok.is(AsmToken::Hash) ||
@@ -5055,41 +5000,33 @@ ARMAsmParser::parseInstSyncBarrierOptOperand(OperandVector &Operands) {
SMLoc Loc = Parser.getTok().getLoc();
const MCExpr *ISBarrierID;
- if (getParser().parseExpression(ISBarrierID)) {
- Error(Loc, "illegal expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(ISBarrierID))
+ return Error(Loc, "illegal expression");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ISBarrierID);
- if (!CE) {
- Error(Loc, "constant expression expected");
- return MatchOperand_ParseFail;
- }
+ if (!CE)
+ return Error(Loc, "constant expression expected");
int Val = CE->getValue();
- if (Val & ~0xf) {
- Error(Loc, "immediate value out of range");
- return MatchOperand_ParseFail;
- }
+ if (Val & ~0xf)
+ return Error(Loc, "immediate value out of range");
Opt = ARM_ISB::RESERVED_0 + Val;
} else
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
Operands.push_back(ARMOperand::CreateInstSyncBarrierOpt(
(ARM_ISB::InstSyncBOpt)Opt, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
-
/// parseProcIFlagsOperand - Try to parse iflags from CPS instruction.
-OperandMatchResultTy
-ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
if (!Tok.is(AsmToken::Identifier))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
StringRef IFlagsStr = Tok.getString();
// An iflags string of "none" is interpreted to mean that none of the AIF
@@ -5106,7 +5043,7 @@ ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
// If some specific iflag is already set, it means that some letter is
// present more than once, this is not acceptable.
if (Flag == ~0U || (IFlags & Flag))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
IFlags |= Flag;
}
@@ -5114,12 +5051,11 @@ ARMAsmParser::parseProcIFlagsOperand(OperandVector &Operands) {
Parser.Lex(); // Eat identifier token.
Operands.push_back(ARMOperand::CreateProcIFlags((ARM_PROC::IFlags)IFlags, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// parseMSRMaskOperand - Try to parse mask flags from MSR instruction.
-OperandMatchResultTy
-ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
@@ -5127,28 +5063,28 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
if (Tok.is(AsmToken::Integer)) {
int64_t Val = Tok.getIntVal();
if (Val > 255 || Val < 0) {
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
}
unsigned SYSmvalue = Val & 0xFF;
Parser.Lex();
Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
if (!Tok.is(AsmToken::Identifier))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
StringRef Mask = Tok.getString();
if (isMClass()) {
auto TheReg = ARMSysReg::lookupMClassSysRegByName(Mask.lower());
if (!TheReg || !TheReg->hasRequiredFeatures(getSTI().getFeatureBits()))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
unsigned SYSmvalue = TheReg->Encoding & 0xFFF;
Parser.Lex(); // Eat identifier token.
Operands.push_back(ARMOperand::CreateMSRMask(SYSmvalue, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
// Split spec_reg from flag, example: CPSR_sxf => "CPSR" and "sxf"
@@ -5172,7 +5108,7 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
if (FlagsVal == ~0U) {
if (!Flags.empty())
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
else
FlagsVal = 8; // No flag
}
@@ -5191,11 +5127,11 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
// If some specific flag is already set, it means that some letter is
// present more than once, this is not acceptable.
if (Flag == ~0U || (FlagsVal & Flag))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
FlagsVal |= Flag;
}
} else // No match for special register.
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
// Special register without flags is NOT equivalent to "fc" flags.
// NOTE: This is a divergence from gas' behavior. Uncommenting the following
@@ -5211,102 +5147,83 @@ ARMAsmParser::parseMSRMaskOperand(OperandVector &Operands) {
Parser.Lex(); // Eat identifier token.
Operands.push_back(ARMOperand::CreateMSRMask(FlagsVal, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// parseBankedRegOperand - Try to parse a banked register (e.g. "lr_irq") for
/// use in the MRS/MSR instructions added to support virtualization.
-OperandMatchResultTy
-ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseBankedRegOperand(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
const AsmToken &Tok = Parser.getTok();
if (!Tok.is(AsmToken::Identifier))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
StringRef RegName = Tok.getString();
auto TheReg = ARMBankedReg::lookupBankedRegByName(RegName.lower());
if (!TheReg)
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
unsigned Encoding = TheReg->Encoding;
Parser.Lex(); // Eat identifier token.
Operands.push_back(ARMOperand::CreateBankedReg(Encoding, S));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
-OperandMatchResultTy
-ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op, int Low,
- int High) {
+ParseStatus ARMAsmParser::parsePKHImm(OperandVector &Operands, StringRef Op,
+ int Low, int High) {
MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok();
- if (Tok.isNot(AsmToken::Identifier)) {
- Error(Parser.getTok().getLoc(), Op + " operand expected.");
- return MatchOperand_ParseFail;
- }
+ if (Tok.isNot(AsmToken::Identifier))
+ return Error(Parser.getTok().getLoc(), Op + " operand expected.");
StringRef ShiftName = Tok.getString();
std::string LowerOp = Op.lower();
std::string UpperOp = Op.upper();
- if (ShiftName != LowerOp && ShiftName != UpperOp) {
- Error(Parser.getTok().getLoc(), Op + " operand expected.");
- return MatchOperand_ParseFail;
- }
+ if (ShiftName != LowerOp && ShiftName != UpperOp)
+ return Error(Parser.getTok().getLoc(), Op + " operand expected.");
Parser.Lex(); // Eat shift type token.
// There must be a '#' and a shift amount.
if (Parser.getTok().isNot(AsmToken::Hash) &&
- Parser.getTok().isNot(AsmToken::Dollar)) {
- Error(Parser.getTok().getLoc(), "'#' expected");
- return MatchOperand_ParseFail;
- }
+ Parser.getTok().isNot(AsmToken::Dollar))
+ return Error(Parser.getTok().getLoc(), "'#' expected");
Parser.Lex(); // Eat hash token.
const MCExpr *ShiftAmount;
SMLoc Loc = Parser.getTok().getLoc();
SMLoc EndLoc;
- if (getParser().parseExpression(ShiftAmount, EndLoc)) {
- Error(Loc, "illegal expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(ShiftAmount, EndLoc))
+ return Error(Loc, "illegal expression");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
- if (!CE) {
- Error(Loc, "constant expression expected");
- return MatchOperand_ParseFail;
- }
+ if (!CE)
+ return Error(Loc, "constant expression expected");
int Val = CE->getValue();
- if (Val < Low || Val > High) {
- Error(Loc, "immediate value out of range");
- return MatchOperand_ParseFail;
- }
+ if (Val < Low || Val > High)
+ return Error(Loc, "immediate value out of range");
Operands.push_back(ARMOperand::CreateImm(CE, Loc, EndLoc));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
-OperandMatchResultTy
-ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok();
SMLoc S = Tok.getLoc();
- if (Tok.isNot(AsmToken::Identifier)) {
- Error(S, "'be' or 'le' operand expected");
- return MatchOperand_ParseFail;
- }
+ if (Tok.isNot(AsmToken::Identifier))
+ return Error(S, "'be' or 'le' operand expected");
int Val = StringSwitch<int>(Tok.getString().lower())
.Case("be", 1)
.Case("le", 0)
.Default(-1);
Parser.Lex(); // Eat the token.
- if (Val == -1) {
- Error(S, "'be' or 'le' operand expected");
- return MatchOperand_ParseFail;
- }
+ if (Val == -1)
+ return Error(S, "'be' or 'le' operand expected");
Operands.push_back(ARMOperand::CreateImm(MCConstantExpr::create(Val,
getContext()),
S, Tok.getEndLoc()));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// parseShifterImm - Parse the shifter immediate operand for SSAT/USAT
@@ -5314,126 +5231,99 @@ ARMAsmParser::parseSetEndImm(OperandVector &Operands) {
/// lsl #n 'n' in [0,31]
/// asr #n 'n' in [1,32]
/// n == 32 encoded as n == 0.
-OperandMatchResultTy
-ARMAsmParser::parseShifterImm(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseShifterImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok();
SMLoc S = Tok.getLoc();
- if (Tok.isNot(AsmToken::Identifier)) {
- Error(S, "shift operator 'asr' or 'lsl' expected");
- return MatchOperand_ParseFail;
- }
+ if (Tok.isNot(AsmToken::Identifier))
+ return Error(S, "shift operator 'asr' or 'lsl' expected");
StringRef ShiftName = Tok.getString();
bool isASR;
if (ShiftName == "lsl" || ShiftName == "LSL")
isASR = false;
else if (ShiftName == "asr" || ShiftName == "ASR")
isASR = true;
- else {
- Error(S, "shift operator 'asr' or 'lsl' expected");
- return MatchOperand_ParseFail;
- }
+ else
+ return Error(S, "shift operator 'asr' or 'lsl' expected");
Parser.Lex(); // Eat the operator.
// A '#' and a shift amount.
if (Parser.getTok().isNot(AsmToken::Hash) &&
- Parser.getTok().isNot(AsmToken::Dollar)) {
- Error(Parser.getTok().getLoc(), "'#' expected");
- return MatchOperand_ParseFail;
- }
+ Parser.getTok().isNot(AsmToken::Dollar))
+ return Error(Parser.getTok().getLoc(), "'#' expected");
Parser.Lex(); // Eat hash token.
SMLoc ExLoc = Parser.getTok().getLoc();
const MCExpr *ShiftAmount;
SMLoc EndLoc;
- if (getParser().parseExpression(ShiftAmount, EndLoc)) {
- Error(ExLoc, "malformed shift expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(ShiftAmount, EndLoc))
+ return Error(ExLoc, "malformed shift expression");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
- if (!CE) {
- Error(ExLoc, "shift amount must be an immediate");
- return MatchOperand_ParseFail;
- }
+ if (!CE)
+ return Error(ExLoc, "shift amount must be an immediate");
int64_t Val = CE->getValue();
if (isASR) {
// Shift amount must be in [1,32]
- if (Val < 1 || Val > 32) {
- Error(ExLoc, "'asr' shift amount must be in range [1,32]");
- return MatchOperand_ParseFail;
- }
+ if (Val < 1 || Val > 32)
+ return Error(ExLoc, "'asr' shift amount must be in range [1,32]");
// asr #32 encoded as asr #0, but is not allowed in Thumb2 mode.
- if (isThumb() && Val == 32) {
- Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
- return MatchOperand_ParseFail;
- }
+ if (isThumb() && Val == 32)
+ return Error(ExLoc, "'asr #32' shift amount not allowed in Thumb mode");
if (Val == 32) Val = 0;
} else {
// Shift amount must be in [1,32]
- if (Val < 0 || Val > 31) {
- Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
- return MatchOperand_ParseFail;
- }
+ if (Val < 0 || Val > 31)
+ return Error(ExLoc, "'lsr' shift amount must be in range [0,31]");
}
Operands.push_back(ARMOperand::CreateShifterImm(isASR, Val, S, EndLoc));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// parseRotImm - Parse the shifter immediate operand for SXTB/UXTB family
/// of instructions. Legal values are:
/// ror #n 'n' in {0, 8, 16, 24}
-OperandMatchResultTy
-ARMAsmParser::parseRotImm(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseRotImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
const AsmToken &Tok = Parser.getTok();
SMLoc S = Tok.getLoc();
if (Tok.isNot(AsmToken::Identifier))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
StringRef ShiftName = Tok.getString();
if (ShiftName != "ror" && ShiftName != "ROR")
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat the operator.
// A '#' and a rotate amount.
if (Parser.getTok().isNot(AsmToken::Hash) &&
- Parser.getTok().isNot(AsmToken::Dollar)) {
- Error(Parser.getTok().getLoc(), "'#' expected");
- return MatchOperand_ParseFail;
- }
+ Parser.getTok().isNot(AsmToken::Dollar))
+ return Error(Parser.getTok().getLoc(), "'#' expected");
Parser.Lex(); // Eat hash token.
SMLoc ExLoc = Parser.getTok().getLoc();
const MCExpr *ShiftAmount;
SMLoc EndLoc;
- if (getParser().parseExpression(ShiftAmount, EndLoc)) {
- Error(ExLoc, "malformed rotate expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(ShiftAmount, EndLoc))
+ return Error(ExLoc, "malformed rotate expression");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
- if (!CE) {
- Error(ExLoc, "rotate amount must be an immediate");
- return MatchOperand_ParseFail;
- }
+ if (!CE)
+ return Error(ExLoc, "rotate amount must be an immediate");
int64_t Val = CE->getValue();
// Shift amount must be in {0, 8, 16, 24} (0 is undocumented extension)
// normally, zero is represented in asm by omitting the rotate operand
// entirely.
- if (Val != 8 && Val != 16 && Val != 24 && Val != 0) {
- Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
- return MatchOperand_ParseFail;
- }
+ if (Val != 8 && Val != 16 && Val != 24 && Val != 0)
+ return Error(ExLoc, "'ror' rotate amount must be 8, 16, or 24");
Operands.push_back(ARMOperand::CreateRotImm(Val, S, EndLoc));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
-OperandMatchResultTy
-ARMAsmParser::parseModImm(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseModImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
MCAsmLexer &Lexer = getLexer();
int64_t Imm1, Imm2;
@@ -5451,14 +5341,14 @@ ARMAsmParser::parseModImm(OperandVector &Operands) {
// mov r0, :lower16:(_foo)
if (Parser.getTok().is(AsmToken::Identifier) ||
Parser.getTok().is(AsmToken::Colon))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
// Hash (dollar) is optional as per the ARMARM
if (Parser.getTok().is(AsmToken::Hash) ||
Parser.getTok().is(AsmToken::Dollar)) {
// Avoid parsing into complex operands (#:)
if (Lexer.peekTok().is(AsmToken::Colon))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
// Eat the hash (dollar)
Parser.Lex();
@@ -5467,10 +5357,8 @@ ARMAsmParser::parseModImm(OperandVector &Operands) {
SMLoc Sx1, Ex1;
Sx1 = Parser.getTok().getLoc();
const MCExpr *Imm1Exp;
- if (getParser().parseExpression(Imm1Exp, Ex1)) {
- Error(Sx1, "malformed expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(Imm1Exp, Ex1))
+ return Error(Sx1, "malformed expression");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Imm1Exp);
@@ -5483,7 +5371,7 @@ ARMAsmParser::parseModImm(OperandVector &Operands) {
Operands.push_back(ARMOperand::CreateModImm((Enc & 0xFF),
(Enc & 0xF00) >> 7,
Sx1, Ex1));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
// We have parsed an immediate which is not for us, fallback to a plain
@@ -5494,25 +5382,22 @@ ARMAsmParser::parseModImm(OperandVector &Operands) {
// parser method is shared, that's why we have to do this here.
if (Parser.getTok().is(AsmToken::EndOfStatement)) {
Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
} else {
// Operands like #(l1 - l2) can only be evaluated at a later stage (via an
// MCFixup). Fallback to a plain immediate.
Operands.push_back(ARMOperand::CreateImm(Imm1Exp, Sx1, Ex1));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
// From this point onward, we expect the input to be a (#bits, #rot) pair
- if (Parser.getTok().isNot(AsmToken::Comma)) {
- Error(Sx1, "expected modified immediate operand: #[0, 255], #even[0-30]");
- return MatchOperand_ParseFail;
- }
+ if (Parser.getTok().isNot(AsmToken::Comma))
+ return Error(Sx1,
+ "expected modified immediate operand: #[0, 255], #even[0-30]");
- if (Imm1 & ~0xFF) {
- Error(Sx1, "immediate operand must a number in the range [0, 255]");
- return MatchOperand_ParseFail;
- }
+ if (Imm1 & ~0xFF)
+ return Error(Sx1, "immediate operand must a number in the range [0, 255]");
// Eat the comma
Parser.Lex();
@@ -5527,10 +5412,8 @@ ARMAsmParser::parseModImm(OperandVector &Operands) {
Parser.Lex();
const MCExpr *Imm2Exp;
- if (getParser().parseExpression(Imm2Exp, Ex2)) {
- Error(Sx2, "malformed expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(Imm2Exp, Ex2))
+ return Error(Sx2, "malformed expression");
CE = dyn_cast<MCConstantExpr>(Imm2Exp);
@@ -5539,93 +5422,72 @@ ARMAsmParser::parseModImm(OperandVector &Operands) {
if (!(Imm2 & ~0x1E)) {
// We have a match!
Operands.push_back(ARMOperand::CreateModImm(Imm1, Imm2, S, Ex2));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
- Error(Sx2, "immediate operand must an even number in the range [0, 30]");
- return MatchOperand_ParseFail;
+ return Error(Sx2,
+ "immediate operand must an even number in the range [0, 30]");
} else {
- Error(Sx2, "constant expression expected");
- return MatchOperand_ParseFail;
+ return Error(Sx2, "constant expression expected");
}
}
-OperandMatchResultTy
-ARMAsmParser::parseBitfield(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseBitfield(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
SMLoc S = Parser.getTok().getLoc();
// The bitfield descriptor is really two operands, the LSB and the width.
if (Parser.getTok().isNot(AsmToken::Hash) &&
- Parser.getTok().isNot(AsmToken::Dollar)) {
- Error(Parser.getTok().getLoc(), "'#' expected");
- return MatchOperand_ParseFail;
- }
+ Parser.getTok().isNot(AsmToken::Dollar))
+ return Error(Parser.getTok().getLoc(), "'#' expected");
Parser.Lex(); // Eat hash token.
const MCExpr *LSBExpr;
SMLoc E = Parser.getTok().getLoc();
- if (getParser().parseExpression(LSBExpr)) {
- Error(E, "malformed immediate expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(LSBExpr))
+ return Error(E, "malformed immediate expression");
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(LSBExpr);
- if (!CE) {
- Error(E, "'lsb' operand must be an immediate");
- return MatchOperand_ParseFail;
- }
+ if (!CE)
+ return Error(E, "'lsb' operand must be an immediate");
int64_t LSB = CE->getValue();
// The LSB must be in the range [0,31]
- if (LSB < 0 || LSB > 31) {
- Error(E, "'lsb' operand must be in the range [0,31]");
- return MatchOperand_ParseFail;
- }
+ if (LSB < 0 || LSB > 31)
+ return Error(E, "'lsb' operand must be in the range [0,31]");
E = Parser.getTok().getLoc();
// Expect another immediate operand.
- if (Parser.getTok().isNot(AsmToken::Comma)) {
- Error(Parser.getTok().getLoc(), "too few operands");
- return MatchOperand_ParseFail;
- }
+ if (Parser.getTok().isNot(AsmToken::Comma))
+ return Error(Parser.getTok().getLoc(), "too few operands");
Parser.Lex(); // Eat hash token.
if (Parser.getTok().isNot(AsmToken::Hash) &&
- Parser.getTok().isNot(AsmToken::Dollar)) {
- Error(Parser.getTok().getLoc(), "'#' expected");
- return MatchOperand_ParseFail;
- }
+ Parser.getTok().isNot(AsmToken::Dollar))
+ return Error(Parser.getTok().getLoc(), "'#' expected");
Parser.Lex(); // Eat hash token.
const MCExpr *WidthExpr;
SMLoc EndLoc;
- if (getParser().parseExpression(WidthExpr, EndLoc)) {
- Error(E, "malformed immediate expression");
- return MatchOperand_ParseFail;
- }
+ if (getParser().parseExpression(WidthExpr, EndLoc))
+ return Error(E, "malformed immediate expression");
CE = dyn_cast<MCConstantExpr>(WidthExpr);
- if (!CE) {
- Error(E, "'width' operand must be an immediate");
- return MatchOperand_ParseFail;
- }
+ if (!CE)
+ return Error(E, "'width' operand must be an immediate");
int64_t Width = CE->getValue();
// The LSB must be in the range [1,32-lsb]
- if (Width < 1 || Width > 32 - LSB) {
- Error(E, "'width' operand must be in the range [1,32-lsb]");
- return MatchOperand_ParseFail;
- }
+ if (Width < 1 || Width > 32 - LSB)
+ return Error(E, "'width' operand must be in the range [1,32-lsb]");
Operands.push_back(ARMOperand::CreateBitfield(LSB, Width, S, EndLoc));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
-OperandMatchResultTy
-ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
// Check for a post-index addressing register operand. Specifically:
// postidx_reg := '+' register {, shift}
// | '-' register {, shift}
// | register {, shift}
- // This method must return MatchOperand_NoMatch without consuming any tokens
+ // This method must return ParseStatus::NoMatch without consuming any tokens
// in the case where there is no match, as other alternatives take other
// parse methods.
MCAsmParser &Parser = getParser();
@@ -5646,9 +5508,8 @@ ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
int Reg = tryParseRegister();
if (Reg == -1) {
if (!haveEaten)
- return MatchOperand_NoMatch;
- Error(Parser.getTok().getLoc(), "register expected");
- return MatchOperand_ParseFail;
+ return ParseStatus::NoMatch;
+ return Error(Parser.getTok().getLoc(), "register expected");
}
ARM_AM::ShiftOpc ShiftTy = ARM_AM::no_shift;
@@ -5656,7 +5517,7 @@ ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
if (Parser.getTok().is(AsmToken::Comma)) {
Parser.Lex(); // Eat the ','.
if (parseMemRegOffsetShift(ShiftTy, ShiftImm))
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
// FIXME: Only approximates end...may include intervening whitespace.
E = Parser.getTok().getLoc();
@@ -5665,11 +5526,10 @@ ARMAsmParser::parsePostIdxReg(OperandVector &Operands) {
Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ShiftTy,
ShiftImm, S, E));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
-OperandMatchResultTy
-ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
// Check for a post-index addressing register operand. Specifically:
// am3offset := '+' register
// | '-' register
@@ -5678,7 +5538,7 @@ ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
// | # + imm
// | # - imm
- // This method must return MatchOperand_NoMatch without consuming any tokens
+ // This method must return ParseStatus::NoMatch without consuming any tokens
// in the case where there is no match, as other alternatives take other
// parse methods.
MCAsmParser &Parser = getParser();
@@ -5695,12 +5555,10 @@ ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
const MCExpr *Offset;
SMLoc E;
if (getParser().parseExpression(Offset, E))
- return MatchOperand_ParseFail;
+ return ParseStatus::Failure;
const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Offset);
- if (!CE) {
- Error(S, "constant expression expected");
- return MatchOperand_ParseFail;
- }
+ if (!CE)
+ return Error(S, "constant expression expected");
// Negative zero is encoded as the flag value
// std::numeric_limits<int32_t>::min().
int32_t Val = CE->getValue();
@@ -5710,7 +5568,7 @@ ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
Operands.push_back(
ARMOperand::CreateImm(MCConstantExpr::create(Val, getContext()), S, E));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
bool haveEaten = false;
@@ -5728,15 +5586,14 @@ ARMAsmParser::parseAM3Offset(OperandVector &Operands) {
int Reg = tryParseRegister();
if (Reg == -1) {
if (!haveEaten)
- return MatchOperand_NoMatch;
- Error(Tok.getLoc(), "register expected");
- return MatchOperand_ParseFail;
+ return ParseStatus::NoMatch;
+ return Error(Tok.getLoc(), "register expected");
}
Operands.push_back(ARMOperand::CreatePostIdxReg(Reg, isAdd, ARM_AM::no_shift,
0, S, Tok.getEndLoc()));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
/// Convert parsed operands to MCInst. Needed here because this instruction
@@ -6086,8 +5943,7 @@ bool ARMAsmParser::parseMemRegOffsetShift(ARM_AM::ShiftOpc &St,
}
/// parseFPImm - A floating point immediate expression operand.
-OperandMatchResultTy
-ARMAsmParser::parseFPImm(OperandVector &Operands) {
+ParseStatus ARMAsmParser::parseFPImm(OperandVector &Operands) {
MCAsmParser &Parser = getParser();
// Anything that can accept a floating point constant as an operand
// needs to go through here, as the regular parseExpression is
@@ -6102,7 +5958,7 @@ ARMAsmParser::parseFPImm(OperandVector &Operands) {
if (Parser.getTok().isNot(AsmToken::Hash) &&
Parser.getTok().isNot(AsmToken::Dollar))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
// Disambiguate the VMOV forms that can accept an FP immediate.
// vmov.f32 <sreg>, #imm
@@ -6122,7 +5978,7 @@ ARMAsmParser::parseFPImm(OperandVector &Operands) {
bool isFconst = Mnemonic.isToken() && (Mnemonic.getToken() == "fconstd" ||
Mnemonic.getToken() == "fconsts");
if (!(isVmovf || isFconst))
- return MatchOperand_NoMatch;
+ return ParseStatus::NoMatch;
Parser.Lex(); // Eat '#' or '$'.
@@ -6143,28 +5999,25 @@ ARMAsmParser::parseFPImm(OperandVector &Operands) {
Operands.push_back(ARMOperand::CreateImm(
MCConstantExpr::create(IntVal, getContext()),
S, Parser.getTok().getLoc()));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
// Also handle plain integers. Instructions which allow floating point
// immediates also allow a raw encoded 8-bit value.
if (Tok.is(AsmToken::Integer) && isFconst) {
int64_t Val = Tok.getIntVal();
Parser.Lex(); // Eat the token.
- if (Val > 255 || Val < 0) {
- Error(Loc, "encoded floating point value out of range");
- return MatchOperand_ParseFail;
- }
+ if (Val > 255 || Val < 0)
+ return Error(Loc, "encoded floating point value out of range");
float RealVal = ARM_AM::getFPImmFloat(Val);
Val = APFloat(RealVal).bitcastToAPInt().getZExtValue();
Operands.push_back(ARMOperand::CreateImm(
MCConstantExpr::create(Val, getContext()), S,
Parser.getTok().getLoc()));
- return MatchOperand_Success;
+ return ParseStatus::Success;
}
- Error(Loc, "invalid floating point immediate");
- return MatchOperand_ParseFail;
+ return Error(Loc, "invalid floating point immediate");
}
/// Parse a arm instruction operand. For now this parses the operand regardless
@@ -6175,13 +6028,13 @@ bool ARMAsmParser::parseOperand(OperandVector &Operands, StringRef Mnemonic) {
// Check if the current operand has a custom associated parser, if so, try to
// custom parse the operand, or fallback to the general approach.
- OperandMatchResultTy ResTy = MatchOperandParserImpl(Operands, Mnemonic);
- if (ResTy == MatchOperand_Success)
+ ParseStatus ResTy = MatchOperandParserImpl(Operands, Mnemonic);
+ if (ResTy.isSuccess())
return false;
// If there wasn't a custom match, try the generic matcher below. Otherwise,
// there was a match, but an error occurred, in which case, just return that
// the operand parsing failed.
- if (ResTy == MatchOperand_ParseFail)
+ if (ResTy.isFailure())
return true;
switch (getLexer().getKind()) {
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