[PATCH] D155229: [RISCV] Add VL nodes and VP patterns for unary zvbb instructions

[Luke Lau via Phabricator via llvm-commits]

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This follows the pattern of lowering VP nodes to equivalent
RISCVISD::*_VL nodes. The nodes are modelled after the VP ISD nodes rather 
than the actual zvbb instructions, and I've included a merge operand to be 
consistent with the underlying pseudos that were recently refactored. They 
also aren't restricted to integers as presumably we can use these for 
floats too later.

I've defined the nodes in RISCVInstrInfoVVLpatterns.td as the nodes aren't Zvk
specific, but the patterns are in RISCVInstrInfoZvk.td.


Repository:
  rG LLVM Github Monorepo

https://reviews.llvm.org/D155229

Files:
  llvm/lib/Target/RISCV/RISCVISelLowering.cpp
  llvm/lib/Target/RISCV/RISCVISelLowering.h
  llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td
  llvm/lib/Target/RISCV/RISCVInstrInfoZvk.td
  llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll
  llvm/test/CodeGen/RISCV/rvv/bswap-vp.ll
  llvm/test/CodeGen/RISCV/rvv/ctlz-vp.ll
  llvm/test/CodeGen/RISCV/rvv/ctpop-vp.ll
  llvm/test/CodeGen/RISCV/rvv/cttz-vp.ll

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