[PATCH] D155228: [AMDGPU] Move SIEncodingFamily into SIDefines.h. NFC.
Stanislav Mekhanoshin via Phabricator via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 13 12:30:09 PDT 2023
rampitec created this revision.
rampitec added reviewers: foad, Joe_Nash.
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I need this for future patch in the MC, while TII is not available
in the llvm-mc. Besides this is not a first time I want it there.
https://reviews.llvm.org/D155228
Files:
llvm/lib/Target/AMDGPU/SIDefines.h
llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
Index: llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
===================================================================
--- llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
+++ llvm/lib/Target/AMDGPU/SIInstrInfo.cpp
@@ -8240,23 +8240,7 @@
return {ImmField, RemainderOffset};
}
-// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
-// and the columns of the getMCOpcodeGen table.
-enum SIEncodingFamily {
- SI = 0,
- VI = 1,
- SDWA = 2,
- SDWA9 = 3,
- GFX80 = 4,
- GFX9 = 5,
- GFX10 = 6,
- SDWA10 = 7,
- GFX90A = 8,
- GFX940 = 9,
- GFX11 = 10,
-};
-
-static SIEncodingFamily subtargetEncodingFamily(const GCNSubtarget &ST) {
+static unsigned subtargetEncodingFamily(const GCNSubtarget &ST) {
switch (ST.getGeneration()) {
default:
break;
@@ -8295,7 +8279,7 @@
}
int SIInstrInfo::pseudoToMCOpcode(int Opcode) const {
- SIEncodingFamily Gen = subtargetEncodingFamily(ST);
+ unsigned Gen = subtargetEncodingFamily(ST);
if ((get(Opcode).TSFlags & SIInstrFlags::renamedInGFX9) != 0 &&
ST.getGeneration() == AMDGPUSubtarget::GFX9)
Index: llvm/lib/Target/AMDGPU/SIDefines.h
===================================================================
--- llvm/lib/Target/AMDGPU/SIDefines.h
+++ llvm/lib/Target/AMDGPU/SIDefines.h
@@ -29,6 +29,24 @@
RegKindMask = (HasVGPR | HasAGPR | HasSGPR)
}; // enum SIRCFlagsr
+namespace SIEncodingFamily {
+// This must be kept in sync with the SIEncodingFamily class in SIInstrInfo.td
+// and the columns of the getMCOpcodeGen table.
+enum {
+ SI = 0,
+ VI = 1,
+ SDWA = 2,
+ SDWA9 = 3,
+ GFX80 = 4,
+ GFX9 = 5,
+ GFX10 = 6,
+ SDWA10 = 7,
+ GFX90A = 8,
+ GFX940 = 9,
+ GFX11 = 10,
+};
+}
+
namespace SIInstrFlags {
// This needs to be kept in sync with the field bits in InstSI.
enum : uint64_t {
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