[llvm] 7b6e606 - [AMDGPU][AsmParser][NFC] Translate parsed MIMG instructions to MCInsts automatically.
Ivan Kosarev via llvm-commits
llvm-commits at lists.llvm.org
Thu Jul 13 11:54:31 PDT 2023
Author: Ivan Kosarev
Date: 2023-07-13T19:47:31+01:00
New Revision: 7b6e606dac3c8a1cfbf9deca2ffe911dd7c3a47d
URL: https://github.com/llvm/llvm-project/commit/7b6e606dac3c8a1cfbf9deca2ffe911dd7c3a47d
DIFF: https://github.com/llvm/llvm-project/commit/7b6e606dac3c8a1cfbf9deca2ffe911dd7c3a47d.diff
LOG: [AMDGPU][AsmParser][NFC] Translate parsed MIMG instructions to MCInsts automatically.
Part of <https://github.com/llvm/llvm-project/issues/62629>.
Reviewed By: foad
Differential Revision: https://reviews.llvm.org/D155061
Added:
Modified:
llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
llvm/lib/Target/AMDGPU/MIMGInstructions.td
Removed:
################################################################################
diff --git a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
index 0569e5834435d6..c493b887257513 100644
--- a/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
+++ b/llvm/lib/Target/AMDGPU/AsmParser/AMDGPUAsmParser.cpp
@@ -1738,10 +1738,6 @@ class AMDGPUAsmParser : public MCTargetAsmParser {
void cvtVOP3Interp(MCInst &Inst, const OperandVector &Operands);
void cvtVINTERP(MCInst &Inst, const OperandVector &Operands);
-
- void cvtMIMG(MCInst &Inst, const OperandVector &Operands,
- bool IsAtomic = false);
- void cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands);
void cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands);
bool parseDimId(unsigned &Encoding);
@@ -7654,60 +7650,9 @@ void AMDGPUAsmParser::cvtMubufImpl(MCInst &Inst,
}
//===----------------------------------------------------------------------===//
-// mimg
+// SMEM
//===----------------------------------------------------------------------===//
-void AMDGPUAsmParser::cvtMIMG(MCInst &Inst, const OperandVector &Operands,
- bool IsAtomic) {
- unsigned I = 1;
- const MCInstrDesc &Desc = MII.get(Inst.getOpcode());
- for (unsigned J = 0; J < Desc.getNumDefs(); ++J) {
- ((AMDGPUOperand &)*Operands[I++]).addRegOperands(Inst, 1);
- }
-
- if (IsAtomic) {
- // Add src, same as dst
- assert(Desc.getNumDefs() == 1);
- ((AMDGPUOperand &)*Operands[I - 1]).addRegOperands(Inst, 1);
- }
-
- OptionalImmIndexMap OptionalIdx;
-
- for (unsigned E = Operands.size(); I != E; ++I) {
- AMDGPUOperand &Op = ((AMDGPUOperand &)*Operands[I]);
-
- // Add the register arguments
- if (Op.isReg()) {
- Op.addRegOperands(Inst, 1);
- } else if (Op.isImmModifier()) {
- OptionalIdx[Op.getImmTy()] = I;
- } else if (!Op.isToken()) {
- llvm_unreachable("unexpected operand type");
- }
- }
-
- bool IsGFX10Plus = isGFX10Plus();
-
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDMask);
- if (IsGFX10Plus)
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDim, -1);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyUNorm);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyCPol);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyR128A16);
- if (IsGFX10Plus)
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyA16);
- if (AMDGPU::hasNamedOperand(Inst.getOpcode(), AMDGPU::OpName::tfe))
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyTFE);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyLWE);
- if (!IsGFX10Plus)
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyDA);
- addOptionalImmOperand(Inst, Operands, OptionalIdx, AMDGPUOperand::ImmTyD16);
-}
-
-void AMDGPUAsmParser::cvtMIMGAtomic(MCInst &Inst, const OperandVector &Operands) {
- cvtMIMG(Inst, Operands, true);
-}
-
void AMDGPUAsmParser::cvtSMEMAtomic(MCInst &Inst, const OperandVector &Operands) {
OptionalImmIndexMap OptionalIdx;
bool IsAtomicReturn = false;
diff --git a/llvm/lib/Target/AMDGPU/MIMGInstructions.td b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
index 7847b97579efce..d924f733624a9a 100644
--- a/llvm/lib/Target/AMDGPU/MIMGInstructions.td
+++ b/llvm/lib/Target/AMDGPU/MIMGInstructions.td
@@ -207,7 +207,6 @@ class MIMG <dag outs, string dns = "">
: MIMG_Base <outs, dns> {
let hasPostISelHook = 1;
- let AsmMatchConverter = "cvtMIMG";
Instruction Opcode = !cast<Instruction>(NAME);
MIMGBaseOpcode BaseOpcode;
@@ -693,7 +692,6 @@ class MIMG_Atomic_gfx6789_base <bits<8> op, string asm, RegisterClass data_rc,
RegisterClass addr_rc, string dns="">
: MIMG_gfx6789 <op, (outs data_rc:$vdst), dns> {
let Constraints = "$vdst = $vdata";
- let AsmMatchConverter = "cvtMIMGAtomic";
let InOperandList = (ins data_rc:$vdata, addr_rc:$vaddr, SReg_256:$srsrc,
DMask:$dmask, UNorm:$unorm, CPol:$cpol,
@@ -705,7 +703,6 @@ class MIMG_Atomic_gfx90a_base <bits<8> op, string asm, RegisterClass data_rc,
RegisterClass addr_rc, string dns="">
: MIMG_gfx90a <op, (outs getLdStRegisterOperand<data_rc>.ret:$vdst), dns> {
let Constraints = "$vdst = $vdata";
- let AsmMatchConverter = "cvtMIMGAtomic";
let InOperandList = (ins getLdStRegisterOperand<data_rc>.ret:$vdata,
addr_rc:$vaddr, SReg_256:$srsrc,
@@ -741,7 +738,6 @@ class MIMG_Atomic_gfx10<mimgopc op, string opcode,
: MIMG_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst),
!if(enableDisasm, "AMDGPU", "")> {
let Constraints = "$vdst = $vdata";
- let AsmMatchConverter = "cvtMIMGAtomic";
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
@@ -755,7 +751,6 @@ class MIMG_Atomic_nsa_gfx10<mimgopc op, string opcode,
: MIMG_nsa_gfx10<!cast<int>(op.GFX10M), (outs DataRC:$vdst), num_addrs,
!if(enableDisasm, "AMDGPU", "")> {
let Constraints = "$vdst = $vdata";
- let AsmMatchConverter = "cvtMIMGAtomic";
let InOperandList = !con((ins DataRC:$vdata),
AddrIns,
@@ -771,7 +766,6 @@ class MIMG_Atomic_gfx11<mimgopc op, string opcode,
: MIMG_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst),
!if(enableDisasm, "AMDGPU", "")> {
let Constraints = "$vdst = $vdata";
- let AsmMatchConverter = "cvtMIMGAtomic";
let InOperandList = (ins DataRC:$vdata, AddrRC:$vaddr0, SReg_256:$srsrc,
DMask:$dmask, Dim:$dim, UNorm:$unorm, CPol:$cpol,
@@ -785,7 +779,6 @@ class MIMG_Atomic_nsa_gfx11<mimgopc op, string opcode,
: MIMG_nsa_gfx11<!cast<int>(op.GFX11), (outs DataRC:$vdst), num_addrs,
!if(enableDisasm, "AMDGPU", "")> {
let Constraints = "$vdst = $vdata";
- let AsmMatchConverter = "cvtMIMGAtomic";
let InOperandList = !con((ins DataRC:$vdata),
AddrIns,
@@ -1228,8 +1221,7 @@ multiclass MIMG_IntersectRay<mimgopc op, string opcode, bit Is64, bit IsA16> {
let BVH = 1;
let A16 = IsA16;
}
- let AsmMatchConverter = "",
- dmask = 0xf,
+ let dmask = 0xf,
unorm = 1,
d16 = 0,
cpol = 0,
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