[PATCH] D155010: [RISCV] Correct resource cycles for vzext/vsext in SiFive7 scheduler.

[Craig Topper via Phabricator via llvm-commits]

This revision was automatically updated to reflect the committed changes.
Closed by commit rG201cf545ad71: [RISCV] Correct resource cycles for vzext/vsext in SiFive7 scheduler. (authored by craig.topper).

Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D155010/new/

https://reviews.llvm.org/D155010

Files:
  llvm/lib/Target/RISCV/RISCVSchedSiFive7.td


Index: llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -51,18 +51,6 @@
   );
 }
 
-class SiFive7GetCyclesOutputLMUL<string mx> {
-  int c = !cond(
-    !eq(mx, "M1") : 1,
-    !eq(mx, "M2") : 2,
-    !eq(mx, "M4") : 4,
-    !eq(mx, "M8") : 8,
-    !eq(mx, "MF2") : 1,
-    !eq(mx, "MF4") : 1,
-    !eq(mx, "MF8") : 1
-  );
-}
-
 class SiFive7GetCyclesVMask<string mx> {
   int c = !cond(
     !eq(mx, "M1") : 1,
@@ -618,7 +606,7 @@
   }
 }
 foreach mx = SchedMxList in {
-  defvar Cycles = SiFive7GetCyclesOutputLMUL<mx>.c;
+  defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
   let Latency = 4, ResourceCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVExtV",      [SiFive7VA], mx, IsWorstCase>;


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