[llvm] 201cf54 - [RISCV] Correct resource cycles for vzext/vsext in SiFive7 scheduler.

[Craig Topper via llvm-commits]

Author: Craig Topper
Date: 2023-07-13T11:37:21-07:00
New Revision: 201cf545ad71f1450f0d26ef3bde5ea25afc28de

URL: https://github.com/llvm/llvm-project/commit/201cf545ad71f1450f0d26ef3bde5ea25afc28de
DIFF: https://github.com/llvm/llvm-project/commit/201cf545ad71f1450f0d26ef3bde5ea25afc28de.diff

LOG: [RISCV] Correct resource cycles for vzext/vsext in SiFive7 scheduler.

The instructions produce DLEN bits per cycle. The vsetvli LMUL for these
instructions is the output EMUL. The input EMUL is scaled down by
the vector factor suffix on the instruction name.

So for LMUL=1 there are 2*DLEN bits of result produced over 2 cycles.
This makes SiFive7GetCyclesDefault the correct resource cycles.

Reviewed By: monkchiang

Differential Revision: https://reviews.llvm.org/D155010

Added: 
    

Modified: 
    llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

Removed: 
    


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diff  --git a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
index 168d2acbfe6803..cbca9e550974e1 100644
--- a/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
+++ b/llvm/lib/Target/RISCV/RISCVSchedSiFive7.td
@@ -51,18 +51,6 @@ class SiFive7GetCyclesNarrowing<string mx> {
   );
 }
 
-class SiFive7GetCyclesOutputLMUL<string mx> {
-  int c = !cond(
-    !eq(mx, "M1") : 1,
-    !eq(mx, "M2") : 2,
-    !eq(mx, "M4") : 4,
-    !eq(mx, "M8") : 8,
-    !eq(mx, "MF2") : 1,
-    !eq(mx, "MF4") : 1,
-    !eq(mx, "MF8") : 1
-  );
-}
-
 class SiFive7GetCyclesVMask<string mx> {
   int c = !cond(
     !eq(mx, "M1") : 1,
@@ -618,7 +606,7 @@ foreach mx = SchedMxList in {
   }
 }
 foreach mx = SchedMxList in {
-  defvar Cycles = SiFive7GetCyclesOutputLMUL<mx>.c;
+  defvar Cycles = SiFive7GetCyclesDefault<mx>.c;
   defvar IsWorstCase = SiFive7IsWorstCaseMX<mx, SchedMxList>.c;
   let Latency = 4, ResourceCycles = [Cycles] in {
     defm "" : LMULWriteResMX<"WriteVExtV",      [SiFive7VA], mx, IsWorstCase>;